From 1239bf67a592777e43856f6448af9c8e423df2a3 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 30 May 2019 16:30:29 +0530 Subject: [PATCH] gpu: nvgpu: add debugger flag for hal.gr.ctxsw_prog unit Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in hal.gr.ctxsw_prog unit Also add this flag for PM context allocation/free Jira NVGPU-3506 Change-Id: Ib40569c7617b8b8aa3343fc89f3d8f30b1d21aa6 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/2132254 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/ctx.c | 24 ++- drivers/gpu/nvgpu/common/gr/ctx_priv.h | 2 + drivers/gpu/nvgpu/common/gr/gr_setup.c | 2 + drivers/gpu/nvgpu/common/gr/subctx.c | 4 + .../nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c | 46 ++--- .../nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c | 48 ++--- .../hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c | 164 +++++++++--------- .../hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h | 32 ++-- .../hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c | 16 +- .../hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h | 6 +- .../hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c | 42 ++--- .../hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h | 10 +- drivers/gpu/nvgpu/hal/init/hal_gm20b.c | 38 ++-- drivers/gpu/nvgpu/hal/init/hal_gp10b.c | 48 ++--- drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 74 ++++---- drivers/gpu/nvgpu/hal/init/hal_tu104.c | 74 ++++---- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 71 ++++---- drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h | 27 +-- drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h | 2 + 19 files changed, 396 insertions(+), 334 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/ctx.c b/drivers/gpu/nvgpu/common/gr/ctx.c index ab9c29081..f24599ca1 100644 --- a/drivers/gpu/nvgpu/common/gr/ctx.c +++ b/drivers/gpu/nvgpu/common/gr/ctx.c @@ -115,7 +115,9 @@ void nvgpu_gr_ctx_free(struct gk20a *g, nvgpu_gr_ctx_unmap_global_ctx_buffers(g, gr_ctx, global_ctx_buffer, vm); +#ifdef CONFIG_NVGPU_DEBUGGER nvgpu_gr_ctx_free_pm_ctx(g, vm, gr_ctx); +#endif nvgpu_gr_ctx_free_patch_ctx(g, vm, gr_ctx); if (nvgpu_mem_is_valid(&gr_ctx->gfxp_rtvcb_ctxsw_buffer)) { @@ -132,6 +134,7 @@ void nvgpu_gr_ctx_free(struct gk20a *g, } } +#ifdef CONFIG_NVGPU_DEBUGGER int nvgpu_gr_ctx_alloc_pm_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_ctx_desc *gr_ctx_desc, @@ -181,6 +184,7 @@ void nvgpu_gr_ctx_free_pm_ctx(struct gk20a *g, struct vm_gk20a *vm, nvgpu_dma_free(g, &pm_ctx->mem); } } +#endif int nvgpu_gr_ctx_alloc_patch_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, @@ -490,6 +494,7 @@ void nvgpu_gr_ctx_set_patch_ctx_data_count(struct nvgpu_gr_ctx *gr_ctx, gr_ctx->patch_ctx.data_count = data_count; } +#ifdef CONFIG_NVGPU_DEBUGGER struct nvgpu_mem *nvgpu_gr_ctx_get_pm_ctx_mem(struct nvgpu_gr_ctx *gr_ctx) { return &gr_ctx->pm_ctx.mem; @@ -504,6 +509,7 @@ u32 nvgpu_gr_ctx_get_pm_ctx_pm_mode(struct nvgpu_gr_ctx *gr_ctx) { return gr_ctx->pm_ctx.pm_mode; } +#endif struct nvgpu_mem *nvgpu_gr_ctx_get_preempt_ctxsw_buffer( struct nvgpu_gr_ctx *gr_ctx) @@ -546,8 +552,10 @@ int nvgpu_gr_ctx_load_golden_ctx_image(struct gk20a *g, struct nvgpu_gr_global_ctx_local_golden_image *local_golden_image, bool cde) { - u64 virt_addr = 0; struct nvgpu_mem *mem; +#ifdef CONFIG_NVGPU_DEBUGGER + u64 virt_addr = 0; +#endif nvgpu_log_fn(g, " "); @@ -560,9 +568,11 @@ int nvgpu_gr_ctx_load_golden_ctx_image(struct gk20a *g, g->ops.gr.ctxsw_prog.init_ctxsw_hdr_data(g, mem); } +#ifdef CONFIG_NVGPU_DEBUGGER if ((g->ops.gr.ctxsw_prog.set_cde_enabled != NULL) && cde) { g->ops.gr.ctxsw_prog.set_cde_enabled(g, mem); } +#endif /* set priv access map */ g->ops.gr.ctxsw_prog.set_priv_access_map_config_mode(g, mem, @@ -574,11 +584,13 @@ int nvgpu_gr_ctx_load_golden_ctx_image(struct gk20a *g, /* disable verif features */ g->ops.gr.ctxsw_prog.disable_verif_features(g, mem); +#ifdef CONFIG_NVGPU_DEBUGGER if (g->ops.gr.ctxsw_prog.set_pmu_options_boost_clock_frequencies != NULL) { g->ops.gr.ctxsw_prog.set_pmu_options_boost_clock_frequencies(g, mem, nvgpu_safe_cast_bool_to_u32(gr_ctx->boosted_ctx)); } +#endif nvgpu_log(g, gpu_dbg_info, "write patch count = %d", gr_ctx->patch_ctx.data_count); @@ -587,6 +599,7 @@ int nvgpu_gr_ctx_load_golden_ctx_image(struct gk20a *g, g->ops.gr.ctxsw_prog.set_patch_addr(g, mem, gr_ctx->patch_ctx.mem.gpu_va); +#ifdef CONFIG_NVGPU_DEBUGGER /* PM ctxt switch is off by default */ gr_ctx->pm_ctx.pm_mode = g->ops.gr.ctxsw_prog.hw_get_pm_mode_no_ctxsw(); @@ -594,6 +607,7 @@ int nvgpu_gr_ctx_load_golden_ctx_image(struct gk20a *g, g->ops.gr.ctxsw_prog.set_pm_mode(g, mem, gr_ctx->pm_ctx.pm_mode); g->ops.gr.ctxsw_prog.set_pm_ptr(g, mem, virt_addr); +#endif return 0; } @@ -685,6 +699,7 @@ void nvgpu_gr_ctx_set_patch_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, } } +#ifdef CONFIG_NVGPU_DEBUGGER u32 nvgpu_gr_ctx_get_ctx_id(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx) { if (!gr_ctx->ctx_id_valid) { @@ -703,6 +718,7 @@ u32 nvgpu_gr_ctx_get_ctx_id(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx) return gr_ctx->ctx_id; } +#endif #ifdef CONFIG_NVGPU_GRAPHICS void nvgpu_gr_ctx_set_zcull_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, @@ -758,6 +774,7 @@ int nvgpu_gr_ctx_zcull_setup(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, } #endif +#ifdef CONFIG_NVGPU_DEBUGGER int nvgpu_gr_ctx_set_smpc_mode(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, bool enable) { @@ -862,6 +879,7 @@ int nvgpu_gr_ctx_set_hwpm_mode(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, return err; } +#endif void nvgpu_gr_ctx_init_compute_preemption_mode(struct nvgpu_gr_ctx *gr_ctx, u32 compute_preempt_mode) @@ -969,7 +987,7 @@ u32 nvgpu_gr_ctx_read_ctx_id(struct nvgpu_gr_ctx *gr_ctx) return gr_ctx->ctx_id; } -#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING +#if defined(CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING) && defined(CONFIG_NVGPU_DEBUGGER) void nvgpu_gr_ctx_set_boosted_ctx(struct nvgpu_gr_ctx *gr_ctx, bool boost) { gr_ctx->boosted_ctx = boost; @@ -991,8 +1009,10 @@ bool nvgpu_gr_ctx_desc_force_preemption_cilp(struct nvgpu_gr_ctx_desc *gr_ctx_de return gr_ctx_desc->force_preemption_cilp; } +#ifdef CONFIG_NVGPU_DEBUGGER bool nvgpu_gr_ctx_desc_dump_ctxsw_stats_on_channel_close( struct nvgpu_gr_ctx_desc *gr_ctx_desc) { return gr_ctx_desc->dump_ctxsw_stats_on_channel_close; } +#endif diff --git a/drivers/gpu/nvgpu/common/gr/ctx_priv.h b/drivers/gpu/nvgpu/common/gr/ctx_priv.h index d95af063a..71e2ba550 100644 --- a/drivers/gpu/nvgpu/common/gr/ctx_priv.h +++ b/drivers/gpu/nvgpu/common/gr/ctx_priv.h @@ -70,7 +70,9 @@ struct nvgpu_gr_ctx { bool golden_img_loaded; bool cilp_preempt_pending; +#ifdef CONFIG_NVGPU_DEBUGGER bool boosted_ctx; +#endif #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION u64 virt_ctx; diff --git a/drivers/gpu/nvgpu/common/gr/gr_setup.c b/drivers/gpu/nvgpu/common/gr/gr_setup.c index 5a344f798..271e29703 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_setup.c +++ b/drivers/gpu/nvgpu/common/gr/gr_setup.c @@ -198,12 +198,14 @@ void nvgpu_gr_setup_free_gr_ctx(struct gk20a *g, nvgpu_log_fn(g, " "); if (gr_ctx != NULL) { +#ifdef CONFIG_NVGPU_DEBUGGER if ((g->ops.gr.ctxsw_prog.dump_ctxsw_stats != NULL) && nvgpu_gr_ctx_desc_dump_ctxsw_stats_on_channel_close( g->gr->gr_ctx_desc)) { g->ops.gr.ctxsw_prog.dump_ctxsw_stats(g, nvgpu_gr_ctx_get_ctx_mem(gr_ctx)); } +#endif nvgpu_gr_ctx_free(g, gr_ctx, g->gr->global_ctx_buffer, vm); } diff --git a/drivers/gpu/nvgpu/common/gr/subctx.c b/drivers/gpu/nvgpu/common/gr/subctx.c index ac29ac41c..2f5a4a112 100644 --- a/drivers/gpu/nvgpu/common/gr/subctx.c +++ b/drivers/gpu/nvgpu/common/gr/subctx.c @@ -101,8 +101,10 @@ void nvgpu_gr_subctx_load_ctx_header(struct gk20a *g, g->ops.gr.ctxsw_prog.set_patch_addr(g, ctxheader, nvgpu_gr_ctx_get_patch_ctx_mem(gr_ctx)->gpu_va); +#ifdef CONFIG_NVGPU_DEBUGGER g->ops.gr.ctxsw_prog.set_pm_ptr(g, ctxheader, nvgpu_gr_ctx_get_pm_ctx_mem(gr_ctx)->gpu_va); +#endif #ifdef CONFIG_NVGPU_GRAPHICS g->ops.gr.ctxsw_prog.set_zcull_ptr(g, ctxheader, @@ -126,12 +128,14 @@ void nvgpu_gr_subctx_zcull_setup(struct gk20a *g, struct nvgpu_gr_subctx *subctx } #endif +#ifdef CONFIG_NVGPU_DEBUGGER void nvgpu_gr_subctx_set_hwpm_mode(struct gk20a *g, struct nvgpu_gr_subctx *subctx, struct nvgpu_gr_ctx *gr_ctx) { g->ops.gr.ctxsw_prog.set_pm_ptr(g, &subctx->ctx_header, nvgpu_gr_ctx_get_pm_ctx_mem(gr_ctx)->gpu_va); } +#endif void nvgpu_gr_subctx_set_patch_ctx(struct gk20a *g, struct nvgpu_gr_subctx *subctx, struct nvgpu_gr_ctx *gr_ctx) diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index 580326054..e7f1e0eb9 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -186,16 +186,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, - .hw_get_gpccs_header_size = - gm20b_ctxsw_prog_hw_get_gpccs_header_size, - .hw_get_extended_buffer_segments_size_in_bytes = - gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes, - .hw_extended_marker_size_in_bytes = - gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes, - .hw_get_perf_counter_control_register_stride = - gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride, - .get_main_image_ctx_id = - gm20b_ctxsw_prog_get_main_image_ctx_id, .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, @@ -207,12 +197,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .is_zcull_mode_separate_buffer = gm20b_ctxsw_prog_is_zcull_mode_separate_buffer, #endif - .set_pm_ptr = gm20b_ctxsw_prog_set_pm_ptr, - .set_pm_mode = gm20b_ctxsw_prog_set_pm_mode, - .set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode, - .hw_get_pm_mode_no_ctxsw = - gm20b_ctxsw_prog_hw_get_pm_mode_no_ctxsw, - .hw_get_pm_mode_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, @@ -220,14 +204,33 @@ static const struct gpu_ops vgpu_gp10b_ops = { gp10b_ctxsw_prog_set_compute_preemption_mode_cilp, .set_graphics_preemption_mode_gfxp = gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp, - .set_cde_enabled = gm20b_ctxsw_prog_set_cde_enabled, - .set_pc_sampling = gm20b_ctxsw_prog_set_pc_sampling, .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_priv_access_map_config_mode, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_priv_access_map_addr, .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, + .set_full_preemption_ptr = + gp10b_ctxsw_prog_set_full_preemption_ptr, +#ifdef CONFIG_NVGPU_DEBUGGER + .hw_get_gpccs_header_size = + gm20b_ctxsw_prog_hw_get_gpccs_header_size, + .hw_get_extended_buffer_segments_size_in_bytes = + gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes, + .hw_extended_marker_size_in_bytes = + gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes, + .hw_get_perf_counter_control_register_stride = + gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride, + .get_main_image_ctx_id = + gm20b_ctxsw_prog_get_main_image_ctx_id, + .set_pm_ptr = gm20b_ctxsw_prog_set_pm_ptr, + .set_pm_mode = gm20b_ctxsw_prog_set_pm_mode, + .set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode, + .hw_get_pm_mode_no_ctxsw = + gm20b_ctxsw_prog_hw_get_pm_mode_no_ctxsw, + .hw_get_pm_mode_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw, + .set_cde_enabled = gm20b_ctxsw_prog_set_cde_enabled, + .set_pc_sampling = gm20b_ctxsw_prog_set_pc_sampling, .check_main_image_header_magic = gm20b_ctxsw_prog_check_main_image_header_magic, .check_local_header_magic = @@ -239,6 +242,9 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, + .set_pmu_options_boost_clock_frequencies = NULL, + .dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats, +#endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, @@ -253,10 +259,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records, .set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr, #endif - .set_pmu_options_boost_clock_frequencies = NULL, - .set_full_preemption_ptr = - gp10b_ctxsw_prog_set_full_preemption_ptr, - .dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats, }, .config = { .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask, diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index 325911795..d2dadda90 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -220,16 +220,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, - .hw_get_gpccs_header_size = - gm20b_ctxsw_prog_hw_get_gpccs_header_size, - .hw_get_extended_buffer_segments_size_in_bytes = - gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes, - .hw_extended_marker_size_in_bytes = - gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes, - .hw_get_perf_counter_control_register_stride = - gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride, - .get_main_image_ctx_id = - gm20b_ctxsw_prog_get_main_image_ctx_id, .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, @@ -241,6 +231,30 @@ static const struct gpu_ops vgpu_gv11b_ops = { .is_zcull_mode_separate_buffer = gm20b_ctxsw_prog_is_zcull_mode_separate_buffer, #endif + .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, + .set_compute_preemption_mode_cta = + gp10b_ctxsw_prog_set_compute_preemption_mode_cta, + .set_compute_preemption_mode_cilp = + gp10b_ctxsw_prog_set_compute_preemption_mode_cilp, + .set_graphics_preemption_mode_gfxp = + gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp, + .set_priv_access_map_config_mode = + gm20b_ctxsw_prog_set_priv_access_map_config_mode, + .set_priv_access_map_addr = + gm20b_ctxsw_prog_set_priv_access_map_addr, + .disable_verif_features = + gm20b_ctxsw_prog_disable_verif_features, +#ifdef CONFIG_NVGPU_DEBUGGER + .hw_get_gpccs_header_size = + gm20b_ctxsw_prog_hw_get_gpccs_header_size, + .hw_get_extended_buffer_segments_size_in_bytes = + gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes, + .hw_extended_marker_size_in_bytes = + gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes, + .hw_get_perf_counter_control_register_stride = + gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride, + .get_main_image_ctx_id = + gm20b_ctxsw_prog_get_main_image_ctx_id, .set_pm_ptr = gv11b_ctxsw_prog_set_pm_ptr, .set_pm_mode = gm20b_ctxsw_prog_set_pm_mode, .set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode, @@ -249,21 +263,8 @@ static const struct gpu_ops vgpu_gv11b_ops = { .hw_get_pm_mode_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw, .hw_get_pm_mode_stream_out_ctxsw = gv11b_ctxsw_prog_hw_get_pm_mode_stream_out_ctxsw, - .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, - .set_compute_preemption_mode_cta = - gp10b_ctxsw_prog_set_compute_preemption_mode_cta, - .set_compute_preemption_mode_cilp = - gp10b_ctxsw_prog_set_compute_preemption_mode_cilp, - .set_graphics_preemption_mode_gfxp = - gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp, .set_cde_enabled = gm20b_ctxsw_prog_set_cde_enabled, .set_pc_sampling = gm20b_ctxsw_prog_set_pc_sampling, - .set_priv_access_map_config_mode = - gm20b_ctxsw_prog_set_priv_access_map_config_mode, - .set_priv_access_map_addr = - gm20b_ctxsw_prog_set_priv_access_map_addr, - .disable_verif_features = - gm20b_ctxsw_prog_disable_verif_features, .check_main_image_header_magic = gm20b_ctxsw_prog_check_main_image_header_magic, .check_local_header_magic = @@ -275,6 +276,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, +#endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c index aed540902..669e9c4fe 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c @@ -34,32 +34,6 @@ u32 gm20b_ctxsw_prog_hw_get_fecs_header_size(void) return ctxsw_prog_fecs_header_v(); } -u32 gm20b_ctxsw_prog_hw_get_gpccs_header_size(void) -{ - return ctxsw_prog_gpccs_header_stride_v(); -} - -u32 gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes(void) -{ - return ctxsw_prog_extended_buffer_segments_size_in_bytes_v(); -} - -u32 gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes(void) -{ - return ctxsw_prog_extended_marker_size_in_bytes_v(); -} - -u32 gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride(void) -{ - return ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); -} - -u32 gm20b_ctxsw_prog_get_main_image_ctx_id(struct gk20a *g, - struct nvgpu_mem *ctx_mem) -{ - return nvgpu_mem_rd(g, ctx_mem, ctxsw_prog_main_image_context_id_o()); -} - u32 gm20b_ctxsw_prog_get_patch_count(struct gk20a *g, struct nvgpu_mem *ctx_mem) { return nvgpu_mem_rd(g, ctx_mem, ctxsw_prog_main_image_patch_count_o()); @@ -108,6 +82,88 @@ bool gm20b_ctxsw_prog_is_zcull_mode_separate_buffer(u32 mode) } #endif +void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, + struct nvgpu_mem *ctx_mem) +{ + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_num_save_ops_o(), 0); + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_num_restore_ops_o(), 0); +} + +void gm20b_ctxsw_prog_set_compute_preemption_mode_cta(struct gk20a *g, + struct nvgpu_mem *ctx_mem) +{ + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_preemption_options_o(), + ctxsw_prog_main_image_preemption_options_control_cta_enabled_f()); +} + +void gm20b_ctxsw_prog_set_priv_access_map_config_mode(struct gk20a *g, + struct nvgpu_mem *ctx_mem, bool allow_all) +{ + if (allow_all) { + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_priv_access_map_config_o(), + ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f()); + } else { + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_priv_access_map_config_o(), + ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f()); + } +} + +void gm20b_ctxsw_prog_set_priv_access_map_addr(struct gk20a *g, + struct nvgpu_mem *ctx_mem, u64 addr) +{ + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_priv_access_map_addr_lo_o(), + u64_lo32(addr)); + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_priv_access_map_addr_hi_o(), + u64_hi32(addr)); +} + +void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g, + struct nvgpu_mem *ctx_mem) +{ + u32 data; + + data = nvgpu_mem_rd(g, ctx_mem, ctxsw_prog_main_image_misc_options_o()); + + data = data & ~ctxsw_prog_main_image_misc_options_verif_features_m(); + data = data | ctxsw_prog_main_image_misc_options_verif_features_disabled_f(); + + nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_misc_options_o(), data); +} + +#ifdef CONFIG_NVGPU_DEBUGGER +u32 gm20b_ctxsw_prog_hw_get_gpccs_header_size(void) +{ + return ctxsw_prog_gpccs_header_stride_v(); +} + +u32 gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes(void) +{ + return ctxsw_prog_extended_buffer_segments_size_in_bytes_v(); +} + +u32 gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes(void) +{ + return ctxsw_prog_extended_marker_size_in_bytes_v(); +} + +u32 gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride(void) +{ + return ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); +} + +u32 gm20b_ctxsw_prog_get_main_image_ctx_id(struct gk20a *g, + struct nvgpu_mem *ctx_mem) +{ + return nvgpu_mem_rd(g, ctx_mem, ctxsw_prog_main_image_context_id_o()); +} + void gm20b_ctxsw_prog_set_pm_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr) { @@ -154,23 +210,6 @@ u32 gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw(void) return ctxsw_prog_main_image_pm_mode_ctxsw_f(); } -void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, - struct nvgpu_mem *ctx_mem) -{ - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_num_save_ops_o(), 0); - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_num_restore_ops_o(), 0); -} - -void gm20b_ctxsw_prog_set_compute_preemption_mode_cta(struct gk20a *g, - struct nvgpu_mem *ctx_mem) -{ - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_preemption_options_o(), - ctxsw_prog_main_image_preemption_options_control_cta_enabled_f()); -} - void gm20b_ctxsw_prog_set_cde_enabled(struct gk20a *g, struct nvgpu_mem *ctx_mem) { @@ -192,44 +231,6 @@ void gm20b_ctxsw_prog_set_pc_sampling(struct gk20a *g, nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_pm_o(), data); } -void gm20b_ctxsw_prog_set_priv_access_map_config_mode(struct gk20a *g, - struct nvgpu_mem *ctx_mem, bool allow_all) -{ - if (allow_all) { - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_priv_access_map_config_o(), - ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f()); - } else { - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_priv_access_map_config_o(), - ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f()); - } -} - -void gm20b_ctxsw_prog_set_priv_access_map_addr(struct gk20a *g, - struct nvgpu_mem *ctx_mem, u64 addr) -{ - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_priv_access_map_addr_lo_o(), - u64_lo32(addr)); - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_priv_access_map_addr_hi_o(), - u64_hi32(addr)); -} - -void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g, - struct nvgpu_mem *ctx_mem) -{ - u32 data; - - data = nvgpu_mem_rd(g, ctx_mem, ctxsw_prog_main_image_misc_options_o()); - - data = data & ~ctxsw_prog_main_image_misc_options_verif_features_m(); - data = data | ctxsw_prog_main_image_misc_options_verif_features_disabled_f(); - - nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_misc_options_o(), data); -} - bool gm20b_ctxsw_prog_check_main_image_header_magic(u32 *context) { u32 magic = *(context + (ctxsw_prog_main_image_magic_value_o() >> 2)); @@ -274,6 +275,7 @@ u32 gm20b_ctxsw_prog_get_local_priv_register_ctl_offset(u32 *context) u32 data = *(context + (ctxsw_prog_local_priv_register_ctl_o() >> 2)); return ctxsw_prog_local_priv_register_ctl_offset_v(data); } +#endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_NVGPU_FECS_TRACE u32 gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp(void) diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h index f2b7a9bb8..25772bded 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h @@ -29,11 +29,6 @@ struct gk20a; struct nvgpu_mem; u32 gm20b_ctxsw_prog_hw_get_fecs_header_size(void); -u32 gm20b_ctxsw_prog_hw_get_gpccs_header_size(void); -u32 gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes(void); -u32 gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes(void); -u32 gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride(void); -u32 gm20b_ctxsw_prog_get_main_image_ctx_id(struct gk20a *g, struct nvgpu_mem *ctx_mem); u32 gm20b_ctxsw_prog_get_patch_count(struct gk20a *g, struct nvgpu_mem *ctx_mem); void gm20b_ctxsw_prog_set_patch_count(struct gk20a *g, struct nvgpu_mem *ctx_mem, u32 count); @@ -48,6 +43,22 @@ void gm20b_ctxsw_prog_set_zcull_mode_no_ctxsw(struct gk20a *g, struct nvgpu_mem *ctx_mem); bool gm20b_ctxsw_prog_is_zcull_mode_separate_buffer(u32 mode); #endif +void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, + struct nvgpu_mem *ctx_mem); +void gm20b_ctxsw_prog_set_compute_preemption_mode_cta(struct gk20a *g, + struct nvgpu_mem *ctx_mem); +void gm20b_ctxsw_prog_set_priv_access_map_config_mode(struct gk20a *g, + struct nvgpu_mem *ctx_mem, bool allow_all); +void gm20b_ctxsw_prog_set_priv_access_map_addr(struct gk20a *g, + struct nvgpu_mem *ctx_mem, u64 addr); +void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g, + struct nvgpu_mem *ctx_mem); +#ifdef CONFIG_NVGPU_DEBUGGER +u32 gm20b_ctxsw_prog_hw_get_gpccs_header_size(void); +u32 gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes(void); +u32 gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes(void); +u32 gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride(void); +u32 gm20b_ctxsw_prog_get_main_image_ctx_id(struct gk20a *g, struct nvgpu_mem *ctx_mem); void gm20b_ctxsw_prog_set_pm_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); void gm20b_ctxsw_prog_set_pm_mode(struct gk20a *g, @@ -56,20 +67,10 @@ void gm20b_ctxsw_prog_set_pm_smpc_mode(struct gk20a *g, struct nvgpu_mem *ctx_mem, bool enable); u32 gm20b_ctxsw_prog_hw_get_pm_mode_no_ctxsw(void); u32 gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw(void); -void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, - struct nvgpu_mem *ctx_mem); -void gm20b_ctxsw_prog_set_compute_preemption_mode_cta(struct gk20a *g, - struct nvgpu_mem *ctx_mem); void gm20b_ctxsw_prog_set_cde_enabled(struct gk20a *g, struct nvgpu_mem *ctx_mem); void gm20b_ctxsw_prog_set_pc_sampling(struct gk20a *g, struct nvgpu_mem *ctx_mem, bool enable); -void gm20b_ctxsw_prog_set_priv_access_map_config_mode(struct gk20a *g, - struct nvgpu_mem *ctx_mem, bool allow_all); -void gm20b_ctxsw_prog_set_priv_access_map_addr(struct gk20a *g, - struct nvgpu_mem *ctx_mem, u64 addr); -void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g, - struct nvgpu_mem *ctx_mem); bool gm20b_ctxsw_prog_check_main_image_header_magic(u32 *context); bool gm20b_ctxsw_prog_check_local_header_magic(u32 *context); u32 gm20b_ctxsw_prog_get_num_gpcs(u32 *context); @@ -78,6 +79,7 @@ void gm20b_ctxsw_prog_get_extended_buffer_size_offset(u32 *context, u32 *size, u32 *offset); void gm20b_ctxsw_prog_get_ppc_info(u32 *context, u32 *num_ppcs, u32 *ppc_mask); u32 gm20b_ctxsw_prog_get_local_priv_register_ctl_offset(u32 *context); +#endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_NVGPU_FECS_TRACE u32 gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp(void); u32 gm20b_ctxsw_prog_hw_get_ts_tag(u64 ts); diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c index 4128a2e07..c7061e903 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c @@ -53,13 +53,6 @@ void gp10b_ctxsw_prog_set_compute_preemption_mode_cilp(struct gk20a *g, ctxsw_prog_main_image_compute_preemption_options_control_cilp_f()); } -void gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies(struct gk20a *g, - struct nvgpu_mem *ctx_mem, u32 boosted_ctx) -{ - u32 data = ctxsw_prog_main_image_pmu_options_boost_clock_frequencies_f(boosted_ctx); - nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_pmu_options_o(), data); -} - void gp10b_ctxsw_prog_set_full_preemption_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr) { @@ -83,6 +76,14 @@ void gp10b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, gm20b_ctxsw_prog_init_ctxsw_hdr_data(g, ctx_mem); } +#ifdef CONFIG_NVGPU_DEBUGGER +void gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies(struct gk20a *g, + struct nvgpu_mem *ctx_mem, u32 boosted_ctx) +{ + u32 data = ctxsw_prog_main_image_pmu_options_boost_clock_frequencies_f(boosted_ctx); + nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_pmu_options_o(), data); +} + void gp10b_ctxsw_prog_dump_ctxsw_stats(struct gk20a *g, struct nvgpu_mem *ctx_mem) { @@ -127,3 +128,4 @@ void gp10b_ctxsw_prog_dump_ctxsw_stats(struct gk20a *g, nvgpu_mem_rd(g, ctx_mem, ctxsw_prog_main_image_compute_preemption_options_o())); } +#endif /* CONFIG_NVGPU_DEBUGGER */ diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h index acac22a9f..23a4d59a7 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h @@ -34,13 +34,15 @@ void gp10b_ctxsw_prog_set_compute_preemption_mode_cta(struct gk20a *g, struct nvgpu_mem *ctx_mem); void gp10b_ctxsw_prog_set_compute_preemption_mode_cilp(struct gk20a *g, struct nvgpu_mem *ctx_mem); -void gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies(struct gk20a *g, - struct nvgpu_mem *ctx_mem, u32 boosted_ctx); void gp10b_ctxsw_prog_set_full_preemption_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); void gp10b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, struct nvgpu_mem *ctx_mem); +#ifdef CONFIG_NVGPU_DEBUGGER +void gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies(struct gk20a *g, + struct nvgpu_mem *ctx_mem, u32 boosted_ctx); void gp10b_ctxsw_prog_dump_ctxsw_stats(struct gk20a *g, struct nvgpu_mem *ctx_mem); +#endif /* CONFIG_NVGPU_DEBUGGER */ #endif /* NVGPU_CTXSW_PROG_GP10B_H */ diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c index a01fd7c42..636311126 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c @@ -39,21 +39,6 @@ void gv11b_ctxsw_prog_set_zcull_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64_hi32(addr)); } -void gv11b_ctxsw_prog_set_pm_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, - u64 addr) -{ - addr = addr >> 8; - nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_pm_ptr_o(), - u64_lo32(addr)); - nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_pm_ptr_hi_o(), - u64_hi32(addr)); -} - -u32 gv11b_ctxsw_prog_hw_get_pm_mode_stream_out_ctxsw(void) -{ - return ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f(); -} - void gv11b_ctxsw_prog_set_full_preemption_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr) { @@ -78,11 +63,6 @@ void gv11b_ctxsw_prog_set_full_preemption_ptr_veid0(struct gk20a *g, u64_hi32(addr)); } -u32 gv11b_ctxsw_prog_hw_get_perf_counter_register_stride(void) -{ - return ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(); -} - void gv11b_ctxsw_prog_set_context_buffer_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr) { @@ -101,3 +81,25 @@ void gv11b_ctxsw_prog_set_type_per_veid_header(struct gk20a *g, ctxsw_prog_main_image_ctl_o(), ctxsw_prog_main_image_ctl_type_per_veid_header_v()); } + +#ifdef CONFIG_NVGPU_DEBUGGER +void gv11b_ctxsw_prog_set_pm_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, + u64 addr) +{ + addr = addr >> 8; + nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_pm_ptr_o(), + u64_lo32(addr)); + nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_pm_ptr_hi_o(), + u64_hi32(addr)); +} + +u32 gv11b_ctxsw_prog_hw_get_pm_mode_stream_out_ctxsw(void) +{ + return ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f(); +} + +u32 gv11b_ctxsw_prog_hw_get_perf_counter_register_stride(void) +{ + return ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(); +} +#endif /* CONFIG_NVGPU_DEBUGGER */ diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h index 3a5d0abb5..b0a5b65ed 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h @@ -27,17 +27,19 @@ void gv11b_ctxsw_prog_set_zcull_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); -void gv11b_ctxsw_prog_set_pm_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, - u64 addr); -u32 gv11b_ctxsw_prog_hw_get_pm_mode_stream_out_ctxsw(void); void gv11b_ctxsw_prog_set_full_preemption_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); void gv11b_ctxsw_prog_set_full_preemption_ptr_veid0(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); -u32 gv11b_ctxsw_prog_hw_get_perf_counter_register_stride(void); void gv11b_ctxsw_prog_set_context_buffer_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); void gv11b_ctxsw_prog_set_type_per_veid_header(struct gk20a *g, struct nvgpu_mem *ctx_mem); +#ifdef CONFIG_NVGPU_DEBUGGER +void gv11b_ctxsw_prog_set_pm_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, + u64 addr); +u32 gv11b_ctxsw_prog_hw_get_pm_mode_stream_out_ctxsw(void); +u32 gv11b_ctxsw_prog_hw_get_perf_counter_register_stride(void); +#endif /* CONFIG_NVGPU_DEBUGGER */ #endif /* NVGPU_CTXSW_PROG_GV11B_H */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index 33b8fc6c8..2b067813d 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -202,16 +202,6 @@ static const struct gpu_ops gm20b_ops = { .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, - .hw_get_gpccs_header_size = - gm20b_ctxsw_prog_hw_get_gpccs_header_size, - .hw_get_extended_buffer_segments_size_in_bytes = - gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes, - .hw_extended_marker_size_in_bytes = - gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes, - .hw_get_perf_counter_control_register_stride = - gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride, - .get_main_image_ctx_id = - gm20b_ctxsw_prog_get_main_image_ctx_id, .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, @@ -223,23 +213,34 @@ static const struct gpu_ops gm20b_ops = { .is_zcull_mode_separate_buffer = gm20b_ctxsw_prog_is_zcull_mode_separate_buffer, #endif /* CONFIG_NVGPU_GRAPHICS */ - .set_pm_ptr = gm20b_ctxsw_prog_set_pm_ptr, - .set_pm_mode = gm20b_ctxsw_prog_set_pm_mode, - .set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode, - .hw_get_pm_mode_no_ctxsw = - gm20b_ctxsw_prog_hw_get_pm_mode_no_ctxsw, - .hw_get_pm_mode_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw, .init_ctxsw_hdr_data = gm20b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gm20b_ctxsw_prog_set_compute_preemption_mode_cta, - .set_cde_enabled = gm20b_ctxsw_prog_set_cde_enabled, - .set_pc_sampling = gm20b_ctxsw_prog_set_pc_sampling, .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_priv_access_map_config_mode, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_priv_access_map_addr, .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, +#ifdef CONFIG_NVGPU_DEBUGGER + .hw_get_gpccs_header_size = + gm20b_ctxsw_prog_hw_get_gpccs_header_size, + .hw_get_extended_buffer_segments_size_in_bytes = + gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes, + .hw_extended_marker_size_in_bytes = + gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes, + .hw_get_perf_counter_control_register_stride = + gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride, + .get_main_image_ctx_id = + gm20b_ctxsw_prog_get_main_image_ctx_id, + .set_pm_ptr = gm20b_ctxsw_prog_set_pm_ptr, + .set_pm_mode = gm20b_ctxsw_prog_set_pm_mode, + .set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode, + .hw_get_pm_mode_no_ctxsw = + gm20b_ctxsw_prog_hw_get_pm_mode_no_ctxsw, + .hw_get_pm_mode_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw, + .set_cde_enabled = gm20b_ctxsw_prog_set_cde_enabled, + .set_pc_sampling = gm20b_ctxsw_prog_set_pc_sampling, .check_main_image_header_magic = gm20b_ctxsw_prog_check_main_image_header_magic, .check_local_header_magic = @@ -251,6 +252,7 @@ static const struct gpu_ops gm20b_ops = { .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, +#endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index 263f875eb..a0a05e6df 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -240,16 +240,6 @@ static const struct gpu_ops gp10b_ops = { .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, - .hw_get_gpccs_header_size = - gm20b_ctxsw_prog_hw_get_gpccs_header_size, - .hw_get_extended_buffer_segments_size_in_bytes = - gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes, - .hw_extended_marker_size_in_bytes = - gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes, - .hw_get_perf_counter_control_register_stride = - gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride, - .get_main_image_ctx_id = - gm20b_ctxsw_prog_get_main_image_ctx_id, .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, @@ -261,12 +251,6 @@ static const struct gpu_ops gp10b_ops = { .is_zcull_mode_separate_buffer = gm20b_ctxsw_prog_is_zcull_mode_separate_buffer, #endif /* CONFIG_NVGPU_GRAPHICS */ - .set_pm_ptr = gm20b_ctxsw_prog_set_pm_ptr, - .set_pm_mode = gm20b_ctxsw_prog_set_pm_mode, - .set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode, - .hw_get_pm_mode_no_ctxsw = - gm20b_ctxsw_prog_hw_get_pm_mode_no_ctxsw, - .hw_get_pm_mode_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, @@ -274,14 +258,33 @@ static const struct gpu_ops gp10b_ops = { gp10b_ctxsw_prog_set_compute_preemption_mode_cilp, .set_graphics_preemption_mode_gfxp = gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp, - .set_cde_enabled = gm20b_ctxsw_prog_set_cde_enabled, - .set_pc_sampling = gm20b_ctxsw_prog_set_pc_sampling, .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_priv_access_map_config_mode, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_priv_access_map_addr, .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, + .set_full_preemption_ptr = + gp10b_ctxsw_prog_set_full_preemption_ptr, +#ifdef CONFIG_NVGPU_DEBUGGER + .hw_get_gpccs_header_size = + gm20b_ctxsw_prog_hw_get_gpccs_header_size, + .hw_get_extended_buffer_segments_size_in_bytes = + gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes, + .hw_extended_marker_size_in_bytes = + gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes, + .hw_get_perf_counter_control_register_stride = + gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride, + .get_main_image_ctx_id = + gm20b_ctxsw_prog_get_main_image_ctx_id, + .set_pm_ptr = gm20b_ctxsw_prog_set_pm_ptr, + .set_pm_mode = gm20b_ctxsw_prog_set_pm_mode, + .set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode, + .hw_get_pm_mode_no_ctxsw = + gm20b_ctxsw_prog_hw_get_pm_mode_no_ctxsw, + .hw_get_pm_mode_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw, + .set_cde_enabled = gm20b_ctxsw_prog_set_cde_enabled, + .set_pc_sampling = gm20b_ctxsw_prog_set_pc_sampling, .check_main_image_header_magic = gm20b_ctxsw_prog_check_main_image_header_magic, .check_local_header_magic = @@ -293,6 +296,10 @@ static const struct gpu_ops gp10b_ops = { .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, + .set_pmu_options_boost_clock_frequencies = + gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies, + .dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats, +#endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, @@ -307,11 +314,6 @@ static const struct gpu_ops gp10b_ops = { .set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records, .set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr, #endif - .set_pmu_options_boost_clock_frequencies = - gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies, - .set_full_preemption_ptr = - gp10b_ctxsw_prog_set_full_preemption_ptr, - .dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats, }, .config = { .get_gpc_tpc_mask = gm20b_gr_config_get_gpc_tpc_mask, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 35b62d537..5a01b4507 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -303,16 +303,6 @@ static const struct gpu_ops gv11b_ops = { .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, - .hw_get_gpccs_header_size = - gm20b_ctxsw_prog_hw_get_gpccs_header_size, - .hw_get_extended_buffer_segments_size_in_bytes = - gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes, - .hw_extended_marker_size_in_bytes = - gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes, - .hw_get_perf_counter_control_register_stride = - gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride, - .get_main_image_ctx_id = - gm20b_ctxsw_prog_get_main_image_ctx_id, .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, @@ -324,6 +314,38 @@ static const struct gpu_ops gv11b_ops = { .is_zcull_mode_separate_buffer = gm20b_ctxsw_prog_is_zcull_mode_separate_buffer, #endif + .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, + .set_compute_preemption_mode_cta = + gp10b_ctxsw_prog_set_compute_preemption_mode_cta, + .set_compute_preemption_mode_cilp = + gp10b_ctxsw_prog_set_compute_preemption_mode_cilp, + .set_graphics_preemption_mode_gfxp = + gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp, + .set_priv_access_map_config_mode = + gm20b_ctxsw_prog_set_priv_access_map_config_mode, + .set_priv_access_map_addr = + gm20b_ctxsw_prog_set_priv_access_map_addr, + .disable_verif_features = + gm20b_ctxsw_prog_disable_verif_features, + .set_full_preemption_ptr = + gv11b_ctxsw_prog_set_full_preemption_ptr, + .set_full_preemption_ptr_veid0 = + gv11b_ctxsw_prog_set_full_preemption_ptr_veid0, + .set_context_buffer_ptr = + gv11b_ctxsw_prog_set_context_buffer_ptr, + .set_type_per_veid_header = + gv11b_ctxsw_prog_set_type_per_veid_header, +#ifdef CONFIG_NVGPU_DEBUGGER + .hw_get_gpccs_header_size = + gm20b_ctxsw_prog_hw_get_gpccs_header_size, + .hw_get_extended_buffer_segments_size_in_bytes = + gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes, + .hw_extended_marker_size_in_bytes = + gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes, + .hw_get_perf_counter_control_register_stride = + gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride, + .get_main_image_ctx_id = + gm20b_ctxsw_prog_get_main_image_ctx_id, .set_pm_ptr = gv11b_ctxsw_prog_set_pm_ptr, .set_pm_mode = gm20b_ctxsw_prog_set_pm_mode, .set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode, @@ -332,21 +354,8 @@ static const struct gpu_ops gv11b_ops = { .hw_get_pm_mode_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw, .hw_get_pm_mode_stream_out_ctxsw = gv11b_ctxsw_prog_hw_get_pm_mode_stream_out_ctxsw, - .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, - .set_compute_preemption_mode_cta = - gp10b_ctxsw_prog_set_compute_preemption_mode_cta, - .set_compute_preemption_mode_cilp = - gp10b_ctxsw_prog_set_compute_preemption_mode_cilp, - .set_graphics_preemption_mode_gfxp = - gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp, .set_cde_enabled = NULL, .set_pc_sampling = gm20b_ctxsw_prog_set_pc_sampling, - .set_priv_access_map_config_mode = - gm20b_ctxsw_prog_set_priv_access_map_config_mode, - .set_priv_access_map_addr = - gm20b_ctxsw_prog_set_priv_access_map_addr, - .disable_verif_features = - gm20b_ctxsw_prog_disable_verif_features, .check_main_image_header_magic = gm20b_ctxsw_prog_check_main_image_header_magic, .check_local_header_magic = @@ -358,6 +367,12 @@ static const struct gpu_ops gv11b_ops = { .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, + .set_pmu_options_boost_clock_frequencies = + gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies, + .hw_get_perf_counter_register_stride = + gv11b_ctxsw_prog_hw_get_perf_counter_register_stride, + .dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats, +#endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, @@ -372,19 +387,6 @@ static const struct gpu_ops gv11b_ops = { .set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records, .set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr, #endif - .set_pmu_options_boost_clock_frequencies = - gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies, - .set_full_preemption_ptr = - gv11b_ctxsw_prog_set_full_preemption_ptr, - .set_full_preemption_ptr_veid0 = - gv11b_ctxsw_prog_set_full_preemption_ptr_veid0, - .hw_get_perf_counter_register_stride = - gv11b_ctxsw_prog_hw_get_perf_counter_register_stride, - .set_context_buffer_ptr = - gv11b_ctxsw_prog_set_context_buffer_ptr, - .set_type_per_veid_header = - gv11b_ctxsw_prog_set_type_per_veid_header, - .dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats, }, .config = { .get_gpc_tpc_mask = gm20b_gr_config_get_gpc_tpc_mask, diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 9ab93be4f..c42df7397 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -336,16 +336,6 @@ static const struct gpu_ops tu104_ops = { .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, - .hw_get_gpccs_header_size = - gm20b_ctxsw_prog_hw_get_gpccs_header_size, - .hw_get_extended_buffer_segments_size_in_bytes = - gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes, - .hw_extended_marker_size_in_bytes = - gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes, - .hw_get_perf_counter_control_register_stride = - gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride, - .get_main_image_ctx_id = - gm20b_ctxsw_prog_get_main_image_ctx_id, .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, @@ -357,6 +347,38 @@ static const struct gpu_ops tu104_ops = { .is_zcull_mode_separate_buffer = gm20b_ctxsw_prog_is_zcull_mode_separate_buffer, #endif + .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, + .set_compute_preemption_mode_cta = + gm20b_ctxsw_prog_set_compute_preemption_mode_cta, + .set_compute_preemption_mode_cilp = + gp10b_ctxsw_prog_set_compute_preemption_mode_cilp, + .set_graphics_preemption_mode_gfxp = + gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp, + .set_priv_access_map_config_mode = + gm20b_ctxsw_prog_set_priv_access_map_config_mode, + .set_priv_access_map_addr = + gm20b_ctxsw_prog_set_priv_access_map_addr, + .disable_verif_features = + gm20b_ctxsw_prog_disable_verif_features, + .set_full_preemption_ptr = + gv11b_ctxsw_prog_set_full_preemption_ptr, + .set_full_preemption_ptr_veid0 = + gv11b_ctxsw_prog_set_full_preemption_ptr_veid0, + .set_context_buffer_ptr = + gv11b_ctxsw_prog_set_context_buffer_ptr, + .set_type_per_veid_header = + gv11b_ctxsw_prog_set_type_per_veid_header, +#ifdef CONFIG_NVGPU_DEBUGGER + .hw_get_gpccs_header_size = + gm20b_ctxsw_prog_hw_get_gpccs_header_size, + .hw_get_extended_buffer_segments_size_in_bytes = + gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes, + .hw_extended_marker_size_in_bytes = + gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes, + .hw_get_perf_counter_control_register_stride = + gm20b_ctxsw_prog_hw_get_perf_counter_control_register_stride, + .get_main_image_ctx_id = + gm20b_ctxsw_prog_get_main_image_ctx_id, .set_pm_ptr = gv11b_ctxsw_prog_set_pm_ptr, .set_pm_mode = gm20b_ctxsw_prog_set_pm_mode, .set_pm_smpc_mode = gm20b_ctxsw_prog_set_pm_smpc_mode, @@ -365,21 +387,8 @@ static const struct gpu_ops tu104_ops = { .hw_get_pm_mode_ctxsw = gm20b_ctxsw_prog_hw_get_pm_mode_ctxsw, .hw_get_pm_mode_stream_out_ctxsw = gv11b_ctxsw_prog_hw_get_pm_mode_stream_out_ctxsw, - .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, - .set_compute_preemption_mode_cta = - gm20b_ctxsw_prog_set_compute_preemption_mode_cta, - .set_compute_preemption_mode_cilp = - gp10b_ctxsw_prog_set_compute_preemption_mode_cilp, - .set_graphics_preemption_mode_gfxp = - gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp, .set_cde_enabled = gm20b_ctxsw_prog_set_cde_enabled, .set_pc_sampling = gm20b_ctxsw_prog_set_pc_sampling, - .set_priv_access_map_config_mode = - gm20b_ctxsw_prog_set_priv_access_map_config_mode, - .set_priv_access_map_addr = - gm20b_ctxsw_prog_set_priv_access_map_addr, - .disable_verif_features = - gm20b_ctxsw_prog_disable_verif_features, .check_main_image_header_magic = gm20b_ctxsw_prog_check_main_image_header_magic, .check_local_header_magic = @@ -391,6 +400,12 @@ static const struct gpu_ops tu104_ops = { .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, + .set_pmu_options_boost_clock_frequencies = + gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies, + .hw_get_perf_counter_register_stride = + gv11b_ctxsw_prog_hw_get_perf_counter_register_stride, + .dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats, +#endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, @@ -405,19 +420,6 @@ static const struct gpu_ops tu104_ops = { .set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records, .set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr, #endif - .set_pmu_options_boost_clock_frequencies = - gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies, - .set_full_preemption_ptr = - gv11b_ctxsw_prog_set_full_preemption_ptr, - .set_full_preemption_ptr_veid0 = - gv11b_ctxsw_prog_set_full_preemption_ptr_veid0, - .hw_get_perf_counter_register_stride = - gv11b_ctxsw_prog_hw_get_perf_counter_register_stride, - .set_context_buffer_ptr = - gv11b_ctxsw_prog_set_context_buffer_ptr, - .set_type_per_veid_header = - gv11b_ctxsw_prog_set_type_per_veid_header, - .dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats, }, .config = { .get_gpc_mask = gm20b_gr_config_get_gpc_mask, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index f9e52c299..05a338f3d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -411,13 +411,6 @@ struct gpu_ops { struct { u32 (*hw_get_fecs_header_size)(void); - u32 (*hw_get_gpccs_header_size)(void); - u32 (*hw_get_extended_buffer_segments_size_in_bytes)(void); - u32 (*hw_extended_marker_size_in_bytes)(void); - u32 (*hw_get_perf_counter_control_register_stride)(void); - u32 (*hw_get_perf_counter_register_stride)(void); - u32 (*get_main_image_ctx_id)(struct gk20a *g, - struct nvgpu_mem *ctx_mem); u32 (*get_patch_count)(struct gk20a *g, struct nvgpu_mem *ctx_mem); void (*set_patch_count)(struct gk20a *g, @@ -433,6 +426,36 @@ struct gpu_ops { struct nvgpu_mem *ctx_mem); bool (*is_zcull_mode_separate_buffer)(u32 mode); #endif + void (*set_compute_preemption_mode_cta)(struct gk20a *g, + struct nvgpu_mem *ctx_mem); + void (*set_compute_preemption_mode_cilp)(struct gk20a *g, + struct nvgpu_mem *ctx_mem); + void (*set_graphics_preemption_mode_gfxp)(struct gk20a *g, + struct nvgpu_mem *ctx_mem); + void (*set_context_buffer_ptr)(struct gk20a *g, + struct nvgpu_mem *ctx_mem, u64 addr); + void (*set_full_preemption_ptr)(struct gk20a *g, + struct nvgpu_mem *ctx_mem, u64 addr); + void (*set_full_preemption_ptr_veid0)(struct gk20a *g, + struct nvgpu_mem *ctx_mem, u64 addr); + void (*set_type_per_veid_header)(struct gk20a *g, + struct nvgpu_mem *ctx_mem); + void (*set_priv_access_map_config_mode)(struct gk20a *g, + struct nvgpu_mem *ctx_mem, bool allow_all); + void (*set_priv_access_map_addr)(struct gk20a *g, + struct nvgpu_mem *ctx_mem, u64 addr); + void (*disable_verif_features)(struct gk20a *g, + struct nvgpu_mem *ctx_mem); + void (*init_ctxsw_hdr_data)(struct gk20a *g, + struct nvgpu_mem *ctx_mem); +#ifdef CONFIG_NVGPU_DEBUGGER + u32 (*hw_get_gpccs_header_size)(void); + u32 (*hw_get_extended_buffer_segments_size_in_bytes)(void); + u32 (*hw_extended_marker_size_in_bytes)(void); + u32 (*hw_get_perf_counter_control_register_stride)(void); + u32 (*hw_get_perf_counter_register_stride)(void); + u32 (*get_main_image_ctx_id)(struct gk20a *g, + struct nvgpu_mem *ctx_mem); void (*set_pm_ptr)(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); void (*set_pm_mode)(struct gk20a *g, @@ -442,24 +465,10 @@ struct gpu_ops { u32 (*hw_get_pm_mode_no_ctxsw)(void); u32 (*hw_get_pm_mode_ctxsw)(void); u32 (*hw_get_pm_mode_stream_out_ctxsw)(void); - void (*init_ctxsw_hdr_data)(struct gk20a *g, - struct nvgpu_mem *ctx_mem); - void (*set_compute_preemption_mode_cta)(struct gk20a *g, - struct nvgpu_mem *ctx_mem); - void (*set_compute_preemption_mode_cilp)(struct gk20a *g, - struct nvgpu_mem *ctx_mem); - void (*set_graphics_preemption_mode_gfxp)(struct gk20a *g, - struct nvgpu_mem *ctx_mem); void (*set_cde_enabled)(struct gk20a *g, struct nvgpu_mem *ctx_mem); void (*set_pc_sampling)(struct gk20a *g, struct nvgpu_mem *ctx_mem, bool enable); - void (*set_priv_access_map_config_mode)(struct gk20a *g, - struct nvgpu_mem *ctx_mem, bool allow_all); - void (*set_priv_access_map_addr)(struct gk20a *g, - struct nvgpu_mem *ctx_mem, u64 addr); - void (*disable_verif_features)(struct gk20a *g, - struct nvgpu_mem *ctx_mem); bool (*check_main_image_header_magic)(u32 *context); bool (*check_local_header_magic)(u32 *context); u32 (*get_num_gpcs)(u32 *context); @@ -469,6 +478,13 @@ struct gpu_ops { void (*get_ppc_info)(u32 *context, u32 *num_ppcs, u32 *ppc_mask); u32 (*get_local_priv_register_ctl_offset)(u32 *context); + + void (*set_pmu_options_boost_clock_frequencies)( + struct gk20a *g, + struct nvgpu_mem *ctx_mem, u32 boosted_ctx); + void (*dump_ctxsw_stats)(struct gk20a *g, + struct nvgpu_mem *ctx_mem); +#endif #ifdef CONFIG_NVGPU_FECS_TRACE u32 (*hw_get_ts_tag_invalid_timestamp)(void); u32 (*hw_get_ts_tag)(u64 ts); @@ -483,19 +499,6 @@ struct gpu_ops { struct nvgpu_mem *ctx_mem, u64 addr, u32 aperture_mask); #endif - void (*set_pmu_options_boost_clock_frequencies)( - struct gk20a *g, - struct nvgpu_mem *ctx_mem, u32 boosted_ctx); - void (*set_context_buffer_ptr)(struct gk20a *g, - struct nvgpu_mem *ctx_mem, u64 addr); - void (*set_full_preemption_ptr)(struct gk20a *g, - struct nvgpu_mem *ctx_mem, u64 addr); - void (*set_full_preemption_ptr_veid0)(struct gk20a *g, - struct nvgpu_mem *ctx_mem, u64 addr); - void (*set_type_per_veid_header)(struct gk20a *g, - struct nvgpu_mem *ctx_mem); - void (*dump_ctxsw_stats)(struct gk20a *g, - struct nvgpu_mem *ctx_mem); } ctxsw_prog; struct { diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h b/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h index 863bcdd32..84cc4c7f4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h @@ -57,7 +57,9 @@ struct zcull_ctx_desc; #endif #define NVGPU_GR_CTX_CTX 0U +#ifdef CONFIG_NVGPU_DEBUGGER #define NVGPU_GR_CTX_PM_CTX 1U +#endif #define NVGPU_GR_CTX_PATCH_CTX 2U #define NVGPU_GR_CTX_PREEMPT_CTXSW 3U #define NVGPU_GR_CTX_SPILL_CTXSW 4U @@ -101,6 +103,7 @@ void nvgpu_gr_ctx_free(struct gk20a *g, struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer, struct vm_gk20a *vm); +#ifdef CONFIG_NVGPU_DEBUGGER int nvgpu_gr_ctx_alloc_pm_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_ctx_desc *gr_ctx_desc, @@ -108,6 +111,7 @@ int nvgpu_gr_ctx_alloc_pm_ctx(struct gk20a *g, u64 gpu_va); void nvgpu_gr_ctx_free_pm_ctx(struct gk20a *g, struct vm_gk20a *vm, struct nvgpu_gr_ctx *gr_ctx); +#endif int nvgpu_gr_ctx_alloc_patch_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, @@ -173,8 +177,6 @@ void nvgpu_gr_ctx_reset_patch_count(struct gk20a *g, void nvgpu_gr_ctx_set_patch_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, bool set_patch_addr); -u32 nvgpu_gr_ctx_get_ctx_id(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx); - #ifdef CONFIG_NVGPU_GRAPHICS void nvgpu_gr_ctx_set_zcull_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, u32 mode, u64 gpu_va); @@ -187,6 +189,9 @@ int nvgpu_gr_ctx_zcull_setup(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, bool set_zcull_ptr); #endif +#ifdef CONFIG_NVGPU_DEBUGGER +u32 nvgpu_gr_ctx_get_ctx_id(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx); + int nvgpu_gr_ctx_set_smpc_mode(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, bool enable); @@ -195,6 +200,15 @@ int nvgpu_gr_ctx_prepare_hwpm_mode(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, int nvgpu_gr_ctx_set_hwpm_mode(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx, bool set_pm_ptr); +#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING +void nvgpu_gr_ctx_set_boosted_ctx(struct nvgpu_gr_ctx *gr_ctx, bool boost); +bool nvgpu_gr_ctx_get_boosted_ctx(struct nvgpu_gr_ctx *gr_ctx); +#endif + +bool nvgpu_gr_ctx_desc_dump_ctxsw_stats_on_channel_close( + struct nvgpu_gr_ctx_desc *gr_ctx_desc); +#endif /* CONFIG_NVGPU_DEBUGGER */ + void nvgpu_gr_ctx_init_compute_preemption_mode(struct nvgpu_gr_ctx *gr_ctx, u32 compute_preempt_mode); u32 nvgpu_gr_ctx_get_compute_preemption_mode(struct nvgpu_gr_ctx *gr_ctx); @@ -229,18 +243,9 @@ void nvgpu_gr_ctx_set_cilp_preempt_pending(struct nvgpu_gr_ctx *gr_ctx, u32 nvgpu_gr_ctx_read_ctx_id(struct nvgpu_gr_ctx *gr_ctx); -#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING -void nvgpu_gr_ctx_set_boosted_ctx(struct nvgpu_gr_ctx *gr_ctx, bool boost); - -bool nvgpu_gr_ctx_get_boosted_ctx(struct nvgpu_gr_ctx *gr_ctx); -#endif - bool nvgpu_gr_ctx_desc_force_preemption_gfxp( struct nvgpu_gr_ctx_desc *gr_ctx_desc); bool nvgpu_gr_ctx_desc_force_preemption_cilp( struct nvgpu_gr_ctx_desc *gr_ctx_desc); -bool nvgpu_gr_ctx_desc_dump_ctxsw_stats_on_channel_close( - struct nvgpu_gr_ctx_desc *gr_ctx_desc); - #endif /* NVGPU_INCLUDE_GR_CTX_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h b/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h index 5014e9639..f7a3643ab 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h @@ -45,8 +45,10 @@ void nvgpu_gr_subctx_zcull_setup(struct gk20a *g, struct nvgpu_gr_subctx *subctx struct nvgpu_gr_ctx *gr_ctx); #endif +#ifdef CONFIG_NVGPU_DEBUGGER void nvgpu_gr_subctx_set_hwpm_mode(struct gk20a *g, struct nvgpu_gr_subctx *subctx, struct nvgpu_gr_ctx *gr_ctx); +#endif void nvgpu_gr_subctx_set_patch_ctx(struct gk20a *g, struct nvgpu_gr_subctx *subctx, struct nvgpu_gr_ctx *gr_ctx);