gpu: nvgpu: gsp: create nvgpu gsp control fifo interface

Changes:
- control fifo file and its build support is done
- Interface to containing control fifo info to be passed to gsp created
- command and function to send fifo info to GSP

NVGPU-8686
NVGPU-8688
NVGPU-8692

Change-Id: I96c59b621ca299f0f4b71e16bd15cad03e719192
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2756560
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>

arch/nvgpu-common.yaml

@@ -339,6 +339,8 @@ gsp_sched:
              common/gsp_scheduler/gsp_scheduler.h,
              common/gsp_scheduler/gsp_runlist.c,
              common/gsp_scheduler/gsp_runlist.h,
+             common/gsp_scheduler/gsp_ctrl_fifo.c,
+             common/gsp_scheduler/gsp_ctrl_fifo.h,
              include/nvgpu/gsp_sched.h ]
 
 gsp_test:

drivers/gpu/nvgpu/Makefile

@@ -443,7 +443,8 @@ nvgpu-$(CONFIG_NVGPU_GSP_SCHEDULER) += \
 	common/gsp_scheduler/ipc/gsp_cmd.o \
 	common/gsp_scheduler/ipc/gsp_msg.o \
 	common/gsp_scheduler/gsp_scheduler.o \
-	common/gsp_scheduler/gsp_runlist.o
+	common/gsp_scheduler/gsp_runlist.o \
+	common/gsp_scheduler/gsp_ctrl_fifo.o
 endif
 
 ifeq ($(CONFIG_NVGPU_GSP_STRESS_TEST),y)

drivers/gpu/nvgpu/Makefile.sources

@@ -202,7 +202,8 @@ srcs += common/gsp/gsp_init.c \
 	common/gsp_scheduler/ipc/gsp_cmd.c \
 	common/gsp_scheduler/ipc/gsp_msg.c \
 	common/gsp_scheduler/gsp_scheduler.c \
-	common/gsp_scheduler/gsp_runlist.c
+	common/gsp_scheduler/gsp_runlist.c \
+	common/gsp_scheduler/gsp_ctrl_fifo.c
 endif
 
 ifeq ($(CONFIG_NVGPU_GSP_STRESS_TEST),1)

drivers/gpu/nvgpu/common/gsp_scheduler/gsp_ctrl_fifo.c

@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/log.h>
+#include <nvgpu/gsp.h>
+#include <nvgpu/gsp_sched.h>
+#include <nvgpu/nvs.h>
+
+#include "gsp_runlist.h"
+#include "gsp_scheduler.h"
+#include "gsp_ctrl_fifo.h"
+#include "ipc/gsp_cmd.h"
+
+#ifdef CONFIG_NVS_PRESENT
+static int gsp_ctrl_fifo_get_queue_info(struct gk20a *g,
+        struct nvgpu_gsp_ctrl_fifo_info *ctrl_fifo, enum queue_type qtype)
+{
+    int err = 0;
+    u8 mask;
+    enum nvgpu_nvs_ctrl_queue_num queue_num;
+    enum nvgpu_nvs_ctrl_queue_direction queue_direction;
+    struct nvgpu_nvs_ctrl_queue *queue;
+
+    nvgpu_gsp_dbg(g, " ");
+
+    switch (qtype) {
+        case CONTROL_QUEUE:
+            mask = NVGPU_NVS_CTRL_FIFO_QUEUE_EXCLUSIVE_CLIENT_WRITE;
+            queue_num = NVGPU_NVS_NUM_CONTROL;
+            queue_direction = NVGPU_NVS_DIR_CLIENT_TO_SCHEDULER;
+            break;
+        case RESPONSE_QUEUE:
+            mask = NVGPU_NVS_CTRL_FIFO_QUEUE_EXCLUSIVE_CLIENT_READ;
+            queue_num = NVGPU_NVS_NUM_CONTROL;
+            queue_direction = NVGPU_NVS_DIR_SCHEDULER_TO_CLIENT;
+            break;
+        default:
+            nvgpu_err(g, "queue type invalid");
+            err = -EINVAL;
+            goto exit;
+    }
+
+    /* below functions will be removed/changed once UMD support is there. */
+    queue = nvgpu_nvs_ctrl_fifo_get_queue(g->sched_ctrl_fifo, queue_num,
+            queue_direction, &mask);
+    if (queue == NULL) {
+        nvgpu_err(g, "queue allocation failed");
+        err = -EFAULT;
+        goto exit;
+    }
+    /* below functions will be removed/changed once UMD support is there. */
+    err = nvgpu_nvs_buffer_alloc(g->sched_ctrl_fifo, NVS_QUEUE_DEFAULT_SIZE,
+            mask, queue);
+    if (err != 0) {
+        nvgpu_err(g, "gsp buffer allocation failed");
+        goto exit;
+    }
+    ctrl_fifo->fifo_addr_lo = u64_lo32(queue->mem.gpu_va);
+    ctrl_fifo->fifo_addr_hi = u64_hi32(queue->mem.gpu_va);
+    ctrl_fifo->queue_size = GSP_CTRL_FIFO_QUEUE_SIZE;
+    ctrl_fifo->queue_entries = GSP_CTRL_FIFO_QUEUE_ENTRIES;
+    ctrl_fifo->qtype  = qtype;
+
+exit:
+    return err;
+
+}
+
+/* get and send the control fifo info to gsp */
+int nvgpu_gsp_sched_send_queue_info(struct gk20a *g, enum queue_type qtype)
+{
+    int err = 0;
+    struct nv_flcn_cmd_gsp cmd = { };
+    struct nvgpu_gsp_ctrl_fifo_info ctrl_fifo = {};
+
+    nvgpu_gsp_dbg(g, " ");
+
+    /* below function will be removed/changed once UMD support is there. */
+    err = gsp_ctrl_fifo_get_queue_info(g, &ctrl_fifo, qtype);
+    if (err != 0) {
+        nvgpu_err(g, "getting fifo queue info failed");
+        goto exit;
+    }
+
+    cmd.cmd.ctrl_fifo.fifo_addr_lo = ctrl_fifo.fifo_addr_lo;
+    cmd.cmd.ctrl_fifo.fifo_addr_hi = ctrl_fifo.fifo_addr_hi;
+    cmd.cmd.ctrl_fifo.queue_size = ctrl_fifo.queue_size;
+    cmd.cmd.ctrl_fifo.qtype = ctrl_fifo.qtype;
+    cmd.cmd.ctrl_fifo.queue_entries = ctrl_fifo.queue_entries;
+
+    err = gsp_send_cmd_and_wait_for_ack(g, &cmd, NV_GSP_UNIT_CONTROL_INFO_SEND,
+            sizeof(struct nvgpu_gsp_ctrl_fifo_info));
+    if (err != 0) {
+        nvgpu_err(g, "sending control fifo queue to GSP failed");
+    }
+
+exit:
+    return err;
+}
+#endif /* CONFIG_NVS_PRESENT*/

drivers/gpu/nvgpu/common/gsp_scheduler/gsp_ctrl_fifo.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GSP_CTRL_FIFO_H
+#define GSP_CTRL_FIFO_H
+
+#define GSP_CTRL_FIFO_QUEUE_SIZE                65536U
+/* (65536 - sizeof(control block)) / sizeof(each message block) */
+#define GSP_CTRL_FIFO_QUEUE_ENTRIES             1022
+
+/*
+ * following indicates the types of queues
+ */
+enum queue_type {
+    CONTROL_QUEUE,
+    RESPONSE_QUEUE,
+    EVENT_QUEUE
+};
+
+struct nvgpu_gsp_ctrl_fifo_info {
+    /*
+     * Start Address of control fifo queue
+     * fifo_addr_lo ->32 bit starting from LSB
+     * fifo_addr_hi ->32 bit from MSB
+     */
+    u32 fifo_addr_lo;
+    u32 fifo_addr_hi;
+    /*
+     * Size of the control fifo queue
+     */
+    u32 queue_size;
+    /* total number of messages present in the queue */
+    u32 queue_entries;
+    /*
+     * queue type indicates the type of queue it is
+     * it can either be a control queue, response queue
+     * or event queue
+     */
+    u32 qtype;
+};
+int nvgpu_gsp_sched_send_queue_info(struct gk20a *g, enum queue_type qtype);
+#endif/* GSP_CTRL_FIFO_H */

drivers/gpu/nvgpu/common/gsp_scheduler/gsp_runlist.c

@@ -87,6 +87,10 @@ static void gsp_handle_cmd_ack(struct gk20a *g, struct nv_flcn_msg_gsp *msg,
 		g->gsp_sched->active_domain = msg->msg.active_domain.active_domain;
 		*command_ack = true;
 		break;
+	case NV_GSP_UNIT_CONTROL_INFO_SEND:
+		nvgpu_gsp_dbg(g, "Reply to NV_GSP_UNIT_CONTROL_INFO_SEND");
+		*command_ack = true;
+		break;
 	default:
 		nvgpu_err(g, "Un-handled response from GSP");
 		*command_ack = false;
@@ -96,7 +100,7 @@ static void gsp_handle_cmd_ack(struct gk20a *g, struct nv_flcn_msg_gsp *msg,
 	(void)status;
 }
 
-static int gsp_send_cmd_and_wait_for_ack(struct gk20a *g,
+int gsp_send_cmd_and_wait_for_ack(struct gk20a *g,
 		struct nv_flcn_cmd_gsp *cmd, u32 unit_id, u32 size)
 {
 	bool command_ack = false;

drivers/gpu/nvgpu/common/gsp_scheduler/gsp_runlist.h

@@ -26,7 +26,8 @@
 #define GSP_SCHED_GR0_DEVICE_ID			0U
 #define GSP_SCHED_ASYNC_CE0_DEVICE_ID	1U
 
-
+struct nv_flcn_cmd_gsp;
+struct gk20a;
 struct nvgpu_gsp_device_info {
 	/*
 	 * Device index
@@ -71,4 +72,6 @@ struct nvgpu_gsp_domain_id {
 	 */
 	u32 domain_id;
 };
+int gsp_send_cmd_and_wait_for_ack(struct gk20a *g,
+		struct nv_flcn_cmd_gsp *cmd, u32 unit_id, u32 size);
 #endif // NVGPU_GSP_RUNLIST

drivers/gpu/nvgpu/common/gsp_scheduler/ipc/gsp_cmd.h

@@ -27,6 +27,7 @@
 #include <nvgpu/gsp_sched.h>
 #include "../gsp_runlist.h"
 #include "gsp_seq.h"
+#include "common/gsp_scheduler/gsp_ctrl_fifo.h"
 
 struct gk20a;
 
@@ -47,7 +48,8 @@ struct gk20a;
 #define NV_GSP_UNIT_STOP_SCHEDULER		0x0AU
 #define NV_GSP_UNIT_QUERY_NO_OF_DOMAINS	0x0BU
 #define NV_GSP_UNIT_QUERY_ACTIVE_DOMAIN	0X0CU
-#define NV_GSP_UNIT_END					0x0DU
+#define NV_GSP_UNIT_CONTROL_INFO_SEND	0X0DU
+#define NV_GSP_UNIT_END					0x0EU
 
 #define GSP_MSG_HDR_SIZE	U32(sizeof(struct gsp_hdr))
 #define GSP_CMD_HDR_SIZE	U32(sizeof(struct gsp_hdr))
@@ -66,6 +68,7 @@ struct nv_flcn_cmd_gsp {
 		struct nvgpu_gsp_device_info device;
 		struct nvgpu_gsp_runlist_info runlist;
 		struct nvgpu_gsp_domain_info domain;
+		struct nvgpu_gsp_ctrl_fifo_info ctrl_fifo;
 	} cmd;
 };