diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h
index f3c68d346..39ad1f8f2 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/channel.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h
@@ -920,7 +920,7 @@ struct nvgpu_channel *nvgpu_channel_from_id__func(
  * a gpfifo and userd to submit some work. It will also need to be
  * bound to a TSG, since standalone channels are not supported.
  *
- * @return ch if channel could be opened, NULL otherwise.
+ * @return channel pointer if channel could be opened, NULL otherwise.
  * @retval NULL if there is not enough resources to allocate and
  *         initialize the channel.
  */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/engines.h b/drivers/gpu/nvgpu/include/nvgpu/engines.h
index f1229b2a0..2a79c903b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/engines.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/engines.h
@@ -194,9 +194,10 @@ u32 nvgpu_engine_act_interrupt_mask(struct gk20a *g, u32 engine_id);
  *   #nvgpu_fifo.num_engines that is used to count total number of valid h/w
  *   engine ids read from device info h/w registers.
  *
- * @return 0 upon success.
- * @retval Valid error codes upon failure to allocate memory or
- *         failure to get engine info from device info h/w registers.
+ * @return 0 upon success, < 0 otherwise.
+ * @retval -ENOMEM upon failure to allocate memory for engine structure.
+ * @retval -EINVAL upon failure to get engine info from device info h/w
+ *         registers.
  */
 int nvgpu_engine_setup_sw(struct gk20a *g);
 /**