From 12bbff3f5a3b3fb4b364da8250824503948be42a Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Fri, 15 Jan 2021 13:55:27 -0800 Subject: [PATCH] gpu: nvgpu: update doxygen for common.fifo Update function return and return value description for nvgpu_channel_open_new and nvgpu_engine_setup_sw as per review comments. Jira NVGPU-6179 Change-Id: Ie9a9c7c3918f22071173ca8b51dee49f3e405df6 Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2471070 (cherry picked from commit cb8ac4e09f3a4803e967987afa2c55d78235149d) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480565 GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions Reviewed-by: Alex Waterman Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/channel.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/engines.h | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h index f3c68d346..39ad1f8f2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/channel.h +++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h @@ -920,7 +920,7 @@ struct nvgpu_channel *nvgpu_channel_from_id__func( * a gpfifo and userd to submit some work. It will also need to be * bound to a TSG, since standalone channels are not supported. * - * @return ch if channel could be opened, NULL otherwise. + * @return channel pointer if channel could be opened, NULL otherwise. * @retval NULL if there is not enough resources to allocate and * initialize the channel. */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/engines.h b/drivers/gpu/nvgpu/include/nvgpu/engines.h index f1229b2a0..2a79c903b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/engines.h +++ b/drivers/gpu/nvgpu/include/nvgpu/engines.h @@ -194,9 +194,10 @@ u32 nvgpu_engine_act_interrupt_mask(struct gk20a *g, u32 engine_id); * #nvgpu_fifo.num_engines that is used to count total number of valid h/w * engine ids read from device info h/w registers. * - * @return 0 upon success. - * @retval Valid error codes upon failure to allocate memory or - * failure to get engine info from device info h/w registers. + * @return 0 upon success, < 0 otherwise. + * @retval -ENOMEM upon failure to allocate memory for engine structure. + * @retval -EINVAL upon failure to get engine info from device info h/w + * registers. */ int nvgpu_engine_setup_sw(struct gk20a *g); /**