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nvgpu: scripts: update runlist interrupt mask

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hw register checker detects and error on local setup by nvdvms team.
register readout in GVS and nvdvms team setup is different.

On Finial System, Checker is expected to run after init
But on GVS, Checker runs as a test case along with test other GPU tests.
This lead to mismatch between local and gvs testing.

register missmatch detected by an hw register checker is not really
an error, its related to information.

There are two cases for updating mask value
1. These interrupts are mainly for sw information not any errors
2. These are temporary values ready from board
   We will update these values again once we get finial list from HW team

so, we can avoid checking bits 4:7, which represents
 * NV_RUNLIST_INTR_0_RUNLIST_IDLE 4U:4U /* RWIVF */
 * NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE 5U:5U /* RWXVF */
 * NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE 6U:6U /* RWXVF */
 * NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE 7U:7U /* RWXVF */

Bug 3912656

Change-Id: I75d1d4737897ef44e78329ed708e86637e8bcf48
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2831273
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Sagar Kadamati
2022-12-20 11:00:32 +00:00
committed by mobile promotions
parent 1dc067c86b
commit 132f9bdab2
2 changed files with 6 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
scripts/checker/hw_register_generator/Makefile
View File

@@ -22,7 +22,7 @@
repo_path := $(abspath $(shell dirname $(lastword $(MAKEFILE_LIST)))/../../../../..)
kernel_path := $(repo_path)/kernel
checker_path := $(repo_path)/qnx/src/resmgrs/nvrm/nvgpu_rmos/checker
checker_path := $(repo_path)/qnx/src/resmgrs/nvrm/nvgpu_rmos/libnvgpu/src/checker
flags := -I$(kernel_path)/nvgpu/drivers/gpu/nvgpu/include

9
scripts/checker/hw_register_generator/hw_register_generator.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -103,7 +103,7 @@ void nvgpu_checker_print_runlist_reg_list(FILE *header)
};
u32 runlist_intr_values[NVGPU_RUNLIST_SIZE] = {
0xf0, 0x30, 0x0, 0x30
0x0, 0x0, 0x0, 0x0
};
u32 runlist_intr_vector_0_values[NVGPU_RUNLIST_SIZE] = {
@@ -137,10 +137,11 @@ void nvgpu_checker_print_runlist_reg_list(FILE *header)
nvgpu_safe_add_u32(runlist_pri_base,
runlist_intr_0_en_clear_tree_r(intr_tree_1)), 0x0);
nvgpu_checker_insert_reg_data(header, "runlist_intr_0_r", -1,
nvgpu_checker_insert_reg_data_with_mask(header,
"runlist_intr_0_r", -1,
nvgpu_safe_add_u32(runlist_pri_base,
runlist_intr_0_r()),
runlist_intr_values[runlist_id]);
runlist_intr_values[runlist_id], 0xFFFFFF0F);
nvgpu_checker_insert_reg_data(header,
"runlist_intr_vectorid_r", intr_tree_0,