diff --git a/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.c
index d0ed8b5f4..88c7f5311 100644
--- a/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.c
@@ -496,3 +496,52 @@ void vgpu_channel_free_ctx_header(struct channel_gk20a *c)
 {
 	vgpu_free_subctx_header(c->g, c->subctx, c->vm, c->virt_ctx);
 }
+
+void vgpu_handle_channel_event(struct gk20a *g,
+			struct tegra_vgpu_channel_event_info *info)
+{
+	struct tsg_gk20a *tsg;
+
+	if (!info->is_tsg) {
+		nvgpu_err(g, "channel event posted");
+		return;
+	}
+
+	if (info->id >= g->fifo.num_channels ||
+		info->event_id >= TEGRA_VGPU_CHANNEL_EVENT_ID_MAX) {
+		nvgpu_err(g, "invalid channel event");
+		return;
+	}
+
+	tsg = &g->fifo.tsg[info->id];
+
+	gk20a_tsg_event_id_post_event(tsg, info->event_id);
+}
+
+void vgpu_channel_abort_cleanup(struct gk20a *g, u32 chid)
+{
+	struct channel_gk20a *ch = gk20a_channel_from_id(g, chid);
+
+	if (ch == NULL) {
+		nvgpu_err(g, "invalid channel id %d", chid);
+		return;
+	}
+
+	gk20a_channel_set_unserviceable(ch);
+	g->ops.fifo.ch_abort_clean_up(ch);
+	gk20a_channel_put(ch);
+}
+
+void vgpu_set_error_notifier(struct gk20a *g,
+		struct tegra_vgpu_channel_set_error_notifier *p)
+{
+	struct channel_gk20a *ch;
+
+	if (p->chid >= g->fifo.num_channels) {
+		nvgpu_err(g, "invalid chid %d", p->chid);
+		return;
+	}
+
+	ch = &g->fifo.channel[p->chid];
+	g->ops.fifo.set_error_notifier(ch, p->error);
+}
diff --git a/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.h b/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.h
index eec22deb2..857781e3f 100644
--- a/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.h
+++ b/drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.h
@@ -30,6 +30,8 @@ struct channel_gk20a;
 struct fifo_gk20a;
 struct tsg_gk20a;
 struct tegra_vgpu_fifo_intr_info;
+struct tegra_vgpu_channel_event_info;
+struct tegra_vgpu_channel_set_error_notifier;
 
 int vgpu_fifo_setup_sw(struct gk20a *g);
 void vgpu_fifo_cleanup_sw(struct gk20a *g);
@@ -58,5 +60,10 @@ void vgpu_tsg_enable(struct tsg_gk20a *tsg);
 int vgpu_set_sm_exception_type_mask(struct channel_gk20a *ch, u32 mask);
 void vgpu_channel_free_ctx_header(struct channel_gk20a *c);
 int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info);
+void vgpu_handle_channel_event(struct gk20a *g,
+			struct tegra_vgpu_channel_event_info *info);
+void vgpu_channel_abort_cleanup(struct gk20a *g, u32 chid);
+void vgpu_set_error_notifier(struct gk20a *g,
+		struct tegra_vgpu_channel_set_error_notifier *p);
 
 #endif /* NVGPU_FIFO_VGPU_H */
diff --git a/drivers/gpu/nvgpu/common/vgpu/vgpu.c b/drivers/gpu/nvgpu/common/vgpu/vgpu.c
index 19a5115b5..ef715a8d5 100644
--- a/drivers/gpu/nvgpu/common/vgpu/vgpu.c
+++ b/drivers/gpu/nvgpu/common/vgpu/vgpu.c
@@ -68,55 +68,6 @@ int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value)
 	return 0;
 }
 
-static void vgpu_handle_channel_event(struct gk20a *g,
-			struct tegra_vgpu_channel_event_info *info)
-{
-	struct tsg_gk20a *tsg;
-
-	if (!info->is_tsg) {
-		nvgpu_err(g, "channel event posted");
-		return;
-	}
-
-	if (info->id >= g->fifo.num_channels ||
-		info->event_id >= TEGRA_VGPU_CHANNEL_EVENT_ID_MAX) {
-		nvgpu_err(g, "invalid channel event");
-		return;
-	}
-
-	tsg = &g->fifo.tsg[info->id];
-
-	gk20a_tsg_event_id_post_event(tsg, info->event_id);
-}
-
-static void vgpu_channel_abort_cleanup(struct gk20a *g, u32 chid)
-{
-	struct channel_gk20a *ch = gk20a_channel_from_id(g, chid);
-
-	if (ch == NULL) {
-		nvgpu_err(g, "invalid channel id %d", chid);
-		return;
-	}
-
-	gk20a_channel_set_unserviceable(ch);
-	g->ops.fifo.ch_abort_clean_up(ch);
-	gk20a_channel_put(ch);
-}
-
-static void vgpu_set_error_notifier(struct gk20a *g,
-		struct tegra_vgpu_channel_set_error_notifier *p)
-{
-	struct channel_gk20a *ch;
-
-	if (p->chid >= g->fifo.num_channels) {
-		nvgpu_err(g, "invalid chid %d", p->chid);
-		return;
-	}
-
-	ch = &g->fifo.channel[p->chid];
-	g->ops.fifo.set_error_notifier(ch, p->error);
-}
-
 void vgpu_remove_support_common(struct gk20a *g)
 {
 	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);