diff --git a/drivers/gpu/nvgpu/gk20a/ltc_common.c b/drivers/gpu/nvgpu/gk20a/ltc_common.c
index 9d534b7b2..e0ab3f9bb 100644
--- a/drivers/gpu/nvgpu/gk20a/ltc_common.c
+++ b/drivers/gpu/nvgpu/gk20a/ltc_common.c
@@ -24,65 +24,6 @@
 #include "gk20a.h"
 #include "gr_gk20a.h"
 
-static int gk20a_determine_L2_size_bytes(struct gk20a *g)
-{
-	const u32 gpuid = GK20A_GPUID(g->gpu_characteristics.arch,
-				      g->gpu_characteristics.impl);
-	u32 lts_per_ltc;
-	u32 ways;
-	u32 sets;
-	u32 bytes_per_line;
-	u32 active_ltcs;
-	u32 cache_size;
-
-	u32 tmp;
-	u32 active_sets_value;
-
-	tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_cfg1_r());
-	ways = hweight32(ltc_ltc0_lts0_tstg_cfg1_active_ways_v(tmp));
-
-	active_sets_value = ltc_ltc0_lts0_tstg_cfg1_active_sets_v(tmp);
-	if (active_sets_value == ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v()) {
-		sets = 64;
-	} else if (active_sets_value ==
-		 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v()) {
-		sets = 32;
-	} else if (active_sets_value ==
-		 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v()) {
-		sets = 16;
-	} else {
-		dev_err(dev_from_gk20a(g),
-			"Unknown constant %u for active sets",
-		       (unsigned)active_sets_value);
-		sets = 0;
-	}
-
-	active_ltcs = g->gr.num_fbps;
-
-	/* chip-specific values */
-	switch (gpuid) {
-	case GK20A_GPUID_GK20A:
-		lts_per_ltc = 1;
-		bytes_per_line = 128;
-		break;
-
-	case GK20A_GPUID_GM20B:
-		lts_per_ltc = 2;
-		bytes_per_line = 128;
-		break;
-
-	default:
-		dev_err(dev_from_gk20a(g), "Unknown GPU id 0x%02x\n",
-			(unsigned)gpuid);
-		lts_per_ltc = 0;
-		bytes_per_line = 0;
-	}
-
-	cache_size = active_ltcs * lts_per_ltc * ways * sets * bytes_per_line;
-
-	return cache_size;
-}
-
 /*
  * Set the maximum number of ways that can have the "EVIST_LAST" class.
  */
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
index 2794b3db2..aa094dc74 100644
--- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
@@ -224,6 +224,47 @@ static void gk20a_mm_g_elpg_flush_locked(struct gk20a *g)
 
 }
 
+static int gk20a_determine_L2_size_bytes(struct gk20a *g)
+{
+	u32 lts_per_ltc;
+	u32 ways;
+	u32 sets;
+	u32 bytes_per_line;
+	u32 active_ltcs;
+	u32 cache_size;
+
+	u32 tmp;
+	u32 active_sets_value;
+
+	tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_cfg1_r());
+	ways = hweight32(ltc_ltc0_lts0_tstg_cfg1_active_ways_v(tmp));
+
+	active_sets_value = ltc_ltc0_lts0_tstg_cfg1_active_sets_v(tmp);
+	if (active_sets_value == ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v()) {
+		sets = 64;
+	} else if (active_sets_value ==
+		 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v()) {
+		sets = 32;
+	} else if (active_sets_value ==
+		 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v()) {
+		sets = 16;
+	} else {
+		dev_err(dev_from_gk20a(g),
+			"Unknown constant %u for active sets",
+		       (unsigned)active_sets_value);
+		sets = 0;
+	}
+
+	active_ltcs = g->gr.num_fbps;
+
+	/* chip-specific values */
+	lts_per_ltc = 1;
+	bytes_per_line = 128;
+	cache_size = active_ltcs * lts_per_ltc * ways * sets * bytes_per_line;
+
+	return cache_size;
+}
+
 void gk20a_init_ltc(struct gpu_ops *gops)
 {
 	gops->ltc.determine_L2_size_bytes = gk20a_determine_L2_size_bytes;
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
index 96e5dbde1..a089b59c9 100644
--- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
@@ -347,10 +347,51 @@ void gm20b_flush_ltc(struct gk20a *g)
 		 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f());
 }
 
+static int gm20b_determine_L2_size_bytes(struct gk20a *g)
+{
+	u32 lts_per_ltc;
+	u32 ways;
+	u32 sets;
+	u32 bytes_per_line;
+	u32 active_ltcs;
+	u32 cache_size;
+
+	u32 tmp;
+	u32 active_sets_value;
+
+	tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_cfg1_r());
+	ways = hweight32(ltc_ltc0_lts0_tstg_cfg1_active_ways_v(tmp));
+
+	active_sets_value = ltc_ltc0_lts0_tstg_cfg1_active_sets_v(tmp);
+	if (active_sets_value == ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v()) {
+		sets = 64;
+	} else if (active_sets_value ==
+		 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v()) {
+		sets = 32;
+	} else if (active_sets_value ==
+		 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v()) {
+		sets = 16;
+	} else {
+		dev_err(dev_from_gk20a(g),
+			"Unknown constant %u for active sets",
+		       (unsigned)active_sets_value);
+		sets = 0;
+	}
+
+	active_ltcs = g->gr.num_fbps;
+
+	/* chip-specific values */
+	lts_per_ltc = 2;
+	bytes_per_line = 128;
+	cache_size = active_ltcs * lts_per_ltc * ways * sets * bytes_per_line;
+
+	return cache_size;
+}
+
 void gm20b_init_ltc(struct gpu_ops *gops)
 {
 	/* Gk20a reused ops. */
-	gops->ltc.determine_L2_size_bytes = gk20a_determine_L2_size_bytes;
+	gops->ltc.determine_L2_size_bytes = gm20b_determine_L2_size_bytes;
 	gops->ltc.set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last;
 	gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry;
 	gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry;