gpu: nvgpu: update GPCCS falcon base addr init

GPCCS falcon base address was being set without invoking hal api. Remove
FALCON_GPCCS_BASE. This patch defines gpu_ops.gr.gpccs_falcon_base_addr
hal api to get this base address.

JIRA NVGPU-1587

Change-Id: Icfa7a26d1bb2d67c81f05a43f6ce906f59706b3d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969431
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/falcon/falcon_gk20a.c

@@ -733,7 +733,7 @@ int gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
 		flcn->is_interrupt_enabled = false;
 		break;
 	case FALCON_ID_GPCCS:
-		flcn->flcn_base = FALCON_GPCCS_BASE;
+		flcn->flcn_base = g->ops.gr.gpccs_falcon_base_addr();
 		flcn->is_falcon_supported = true;
 		flcn->is_interrupt_enabled = false;
 		break;

drivers/gpu/nvgpu/common/falcon/falcon_gp106.c

@@ -76,7 +76,7 @@ int gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
 		flcn->is_interrupt_enabled = false;
 		break;
 	case FALCON_ID_GPCCS:
-		flcn->flcn_base = FALCON_GPCCS_BASE;
+		flcn->flcn_base = g->ops.gr.gpccs_falcon_base_addr();
 		flcn->is_falcon_supported = true;
 		flcn->is_interrupt_enabled = false;
 		break;

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -8686,3 +8686,8 @@ u32 gr_gk20a_fecs_falcon_base_addr(void)
 {
 	return gr_fecs_irqsset_r();
 }
+
+u32 gr_gk20a_gpccs_falcon_base_addr(void)
+{
+	return gr_gpcs_gpccs_irqsset_r();
+}

drivers/gpu/nvgpu/gk20a/gr_gk20a.h

@@ -798,4 +798,5 @@ void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr);
 
 u32 gk20a_gr_get_fecs_ctx_state_store_major_rev_id(struct gk20a *g);
 u32 gr_gk20a_fecs_falcon_base_addr(void);
+u32 gr_gk20a_gpccs_falcon_base_addr(void);
 #endif /*__GR_GK20A_H__*/

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -234,6 +234,7 @@ static const struct gpu_ops gm20b_ops = {
 		.init_fs_state = gr_gm20b_init_fs_state,
 		.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
 		.fecs_falcon_base_addr = gr_gk20a_fecs_falcon_base_addr,
+		.gpccs_falcon_base_addr = gr_gk20a_gpccs_falcon_base_addr,
 		.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
 		.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
 		.set_gpc_tpc_mask = gr_gm20b_set_gpc_tpc_mask,

drivers/gpu/nvgpu/gp106/gr_gp106.c

@@ -261,3 +261,8 @@ u32 gr_gp106_fecs_falcon_base_addr(void)
 {
 	return gr_fecs_irqsset_r();
 }
+
+u32 gr_gp106_gpccs_falcon_base_addr(void)
+{
+	return gr_gpcs_gpccs_irqsset_r();
+}

drivers/gpu/nvgpu/gp106/gr_gp106.h

@@ -41,5 +41,6 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
 				u32 graphics_preempt_mode,
 				u32 compute_preempt_mode);
 u32 gr_gp106_fecs_falcon_base_addr(void);
+u32 gr_gp106_gpccs_falcon_base_addr(void);
 
 #endif /* NVGPU_GR_GP106_H */

drivers/gpu/nvgpu/gp106/hal_gp106.c

@@ -298,6 +298,7 @@ static const struct gpu_ops gp106_ops = {
 		.init_fs_state = gr_gp10b_init_fs_state,
 		.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
 		.fecs_falcon_base_addr = gr_gp106_fecs_falcon_base_addr,
+		.gpccs_falcon_base_addr = gr_gp106_gpccs_falcon_base_addr,
 		.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
 		.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask,
 		.get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -253,6 +253,7 @@ static const struct gpu_ops gp10b_ops = {
 		.init_fs_state = gr_gp10b_init_fs_state,
 		.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
 		.fecs_falcon_base_addr = gr_gk20a_fecs_falcon_base_addr,
+		.gpccs_falcon_base_addr = gr_gk20a_gpccs_falcon_base_addr,
 		.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
 		.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
 		.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask,

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -356,6 +356,7 @@ static const struct gpu_ops gv100_ops = {
 		.init_fs_state = gr_gv11b_init_fs_state,
 		.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
 		.fecs_falcon_base_addr = gr_gp106_fecs_falcon_base_addr,
+		.gpccs_falcon_base_addr = gr_gp106_gpccs_falcon_base_addr,
 		.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
 		.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode,
 		.set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask,

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -306,6 +306,7 @@ static const struct gpu_ops gv11b_ops = {
 		.init_fs_state = gr_gv11b_init_fs_state,
 		.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
 		.fecs_falcon_base_addr = gr_gk20a_fecs_falcon_base_addr,
+		.gpccs_falcon_base_addr = gr_gk20a_gpccs_falcon_base_addr,
 		.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
 		.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
 		.set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask,

drivers/gpu/nvgpu/include/nvgpu/falcon.h

@@ -39,11 +39,6 @@
 #define FALCON_ID_END	    (11U)
 #define FALCON_ID_INVALID   0xFFFFFFFFU
 
-/*
- * Falcon Base address Defines
- */
-#define FALCON_GPCCS_BASE  0x0041a000U
-
 /* Falcon Register index */
 #define FALCON_REG_R0		(0U)
 #define FALCON_REG_R1		(1U)

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -623,6 +623,7 @@ struct gpu_ops {
 				struct nvgpu_mem *ctx_mem);
 		} ctxsw_prog;
 		u32 (*fecs_falcon_base_addr)(void);
+		u32 (*gpccs_falcon_base_addr)(void);
 	} gr;
 	struct {
 		void (*init_hw)(struct gk20a *g);

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -371,6 +371,7 @@ static const struct gpu_ops tu104_ops = {
 		.init_fs_state = gr_gv11b_init_fs_state,
 		.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
 		.fecs_falcon_base_addr = gr_gp106_fecs_falcon_base_addr,
+		.gpccs_falcon_base_addr = gr_gp106_gpccs_falcon_base_addr,
 		.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
 		.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode,
 		.set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask,