From 14a71cb25a51df34bb18059bccacdb43c2be4f8b Mon Sep 17 00:00:00 2001 From: Vinod G Date: Wed, 17 Apr 2019 18:24:17 -0700 Subject: [PATCH] gpu: nvgpu: add esr_bpt_pending_events hal Add esr_bpt_pending_events hal to report the type of esr_bpt_pending_events to isr to process. Add hal functions in gr instead of moving to gr.intr unit, as it is part of non safety code. JIRA NVGPU-1891 Change-Id: I70d75686042f97aa0e820d7982e95354971c9074 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/2100669 Reviewed-by: svc-mobile-coverity Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 18 ++++++++---------- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 14 +++++++------- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 21 +++++++++++++++++++++ drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 3 +-- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 21 +++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 + drivers/gpu/nvgpu/hal/init/hal_gm20b.c | 1 + drivers/gpu/nvgpu/hal/init/hal_gp10b.c | 1 + drivers/gpu/nvgpu/hal/init/hal_gv100.c | 1 + drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 1 + drivers/gpu/nvgpu/hal/init/hal_tu104.c | 1 + drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 1 + 12 files changed, 65 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index d2aa93cc2..1782d37af 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -492,8 +492,8 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, * * Do not disable exceptions if the only SM exception is BPT_INT */ - if ((global_esr == gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) - && (warp_esr == 0U)) { + if ((g->ops.gr.esr_bpt_pending_events(global_esr, + NVGPU_EVENT_ID_BPT_INT)) && (warp_esr == 0U)) { disable_sm_exceptions = false; } @@ -535,20 +535,18 @@ void gk20a_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, *esr_sm_sel = 1; } -static int gk20a_gr_post_bpt_events(struct gk20a *g, struct tsg_gk20a *tsg, +void gr_intr_post_bpt_events(struct gk20a *g, struct tsg_gk20a *tsg, u32 global_esr) { - if ((global_esr & - gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) != 0U) { + if (g->ops.gr.esr_bpt_pending_events(global_esr, + NVGPU_EVENT_ID_BPT_INT)) { g->ops.tsg.post_event_id(tsg, NVGPU_EVENT_ID_BPT_INT); } - if ((global_esr & - gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f()) != 0U) { + if (g->ops.gr.esr_bpt_pending_events(global_esr, + NVGPU_EVENT_ID_BPT_PAUSE)) { g->ops.tsg.post_event_id(tsg, NVGPU_EVENT_ID_BPT_PAUSE); } - - return 0; } int gk20a_gr_isr(struct gk20a *g) @@ -736,7 +734,7 @@ int gk20a_gr_isr(struct gk20a *g) /* Posting of BPT events should be the last thing in this function */ if ((global_esr != 0U) && (tsg != NULL) && (need_reset == false)) { - gk20a_gr_post_bpt_events(g, tsg, global_esr); + gr_intr_post_bpt_events(g, tsg, global_esr); } if (ch != NULL) { diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index f81f1ac89..21e538693 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -51,13 +51,13 @@ enum { }; enum { - NVGPU_EVENT_ID_BPT_INT = 0, - NVGPU_EVENT_ID_BPT_PAUSE, - NVGPU_EVENT_ID_BLOCKING_SYNC, - NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED, - NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE, - NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN, - NVGPU_EVENT_ID_MAX, + NVGPU_EVENT_ID_BPT_INT = 0U, + NVGPU_EVENT_ID_BPT_PAUSE = 1U, + NVGPU_EVENT_ID_BLOCKING_SYNC = 2U, + NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED = 3U, + NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE = 4U, + NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN = 5U, + NVGPU_EVENT_ID_MAX = 6U, }; struct gr_channel_map_tlb_entry { diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 11999bca7..fe44597c5 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -767,3 +767,24 @@ void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable) gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl); gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val); } + +bool gm20b_gr_esr_bpt_pending_events(u32 global_esr, u32 bpt_event) +{ + bool ret = false; + + if (bpt_event == NVGPU_EVENT_ID_BPT_INT) { + if ((global_esr & + gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) != 0U) { + ret = true; + } + } + + if (bpt_event == NVGPU_EVENT_ID_BPT_PAUSE) { + if ((global_esr & + gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f()) != 0U) { + ret = true; + } + } + + return ret; +} diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index ab229c7e7..18c96771e 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h @@ -28,8 +28,6 @@ struct gk20a; struct nvgpu_warpstate; - - #define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc #define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280 #define NVB197_SET_SHADER_EXCEPTIONS 0x1528 @@ -76,4 +74,5 @@ void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, u32 global_esr); u32 gr_gm20b_get_pmm_per_chiplet_offset(void); void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable); +bool gm20b_gr_esr_bpt_pending_events(u32 global_esr, u32 bpt_event); #endif /* NVGPU_GM20B_GR_GM20B_H */ diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index cbd101350..ba3a99e7a 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -3203,3 +3203,24 @@ fail: nvgpu_mutex_release(&g->dbg_sessions_lock); return err; } + +bool gv11b_gr_esr_bpt_pending_events(u32 global_esr, u32 bpt_event) +{ + bool ret = false; + + if (bpt_event == NVGPU_EVENT_ID_BPT_INT) { + if ((global_esr & + gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()) != 0U) { + ret = true; + } + } + + if (bpt_event == NVGPU_EVENT_ID_BPT_PAUSE) { + if ((global_esr & + gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f()) != 0U) { + ret = true; + } + } + + return ret; +} diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index bb9a63063..1d7723090 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -172,4 +172,5 @@ void gr_gv11b_set_skedcheck(struct gk20a *g, u32 data); void gr_gv11b_set_go_idle_timeout(struct gk20a *g, u32 data); void gr_gv11b_set_coalesce_buffer_size(struct gk20a *g, u32 data); void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data); +bool gv11b_gr_esr_bpt_pending_events(u32 global_esr, u32 bpt_event); #endif /* NVGPU_GR_GV11B_H */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index e99781ccf..e311c8849 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -300,6 +300,7 @@ static const struct gpu_ops gm20b_ops = { .set_debug_mode = gm20b_gr_set_debug_mode, .log_mme_exception = NULL, .reset = nvgpu_gr_reset, + .esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events, .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index 66e39c23e..5419beff1 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -337,6 +337,7 @@ static const struct gpu_ops gp10b_ops = { .set_debug_mode = gm20b_gr_set_debug_mode, .log_mme_exception = NULL, .reset = nvgpu_gr_reset, + .esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events, .ecc = { .detect = gp10b_ecc_detect_enabled_units, .init = gp10b_ecc_init, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv100.c b/drivers/gpu/nvgpu/hal/init/hal_gv100.c index 945d221e4..5b7fbeb8f 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv100.c @@ -450,6 +450,7 @@ static const struct gpu_ops gv100_ops = { .set_debug_mode = gm20b_gr_set_debug_mode, .log_mme_exception = NULL, .reset = nvgpu_gr_reset, + .esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events, .ctxsw_prog = { .hw_get_fecs_header_size = gm20b_ctxsw_prog_hw_get_fecs_header_size, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 2f1a241e6..054e16b5d 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -425,6 +425,7 @@ static const struct gpu_ops gv11b_ops = { .get_ctxsw_checksum_mismatch_mailbox_val = gr_gv11b_ctxsw_checksum_mismatch_mailbox_val, .reset = nvgpu_gr_reset, + .esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events, .ecc = { .detect = gv11b_ecc_detect_enabled_units, .init = gv11b_ecc_init, diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 1e376cd38..093a2fd72 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -472,6 +472,7 @@ static const struct gpu_ops tu104_ops = { .set_debug_mode = gm20b_gr_set_debug_mode, .log_mme_exception = gr_tu104_log_mme_exception, .reset = nvgpu_gr_reset, + .esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events, .ecc = { .detect = NULL, .init = tu104_ecc_init, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 4e1dc1bf1..58c53016f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -421,6 +421,7 @@ struct gpu_ops { void (*set_debug_mode)(struct gk20a *g, bool enable); void (*log_mme_exception)(struct gk20a *g); int (*reset)(struct gk20a *g); + bool (*esr_bpt_pending_events)(u32 global_esr, u32 bpt_event); struct { void (*detect)(struct gk20a *g); int (*init)(struct gk20a *g);