diff --git a/arch/nvgpu-hal-new.yaml b/arch/nvgpu-hal-new.yaml index 2e423ae05..ab95f35d0 100644 --- a/arch/nvgpu-hal-new.yaml +++ b/arch/nvgpu-hal-new.yaml @@ -112,11 +112,9 @@ priv_ring: ptimer_fusa: safe: yes - owner: Terje B + owner: Sagar Kamble sources: [ hal/ptimer/ptimer_gk20a_fusa.c, - hal/ptimer/ptimer_gk20a.h, - hal/ptimer/ptimer_ga10b_fusa.c, - hal/ptimer/ptimer_ga10b.h ] + hal/ptimer/ptimer_gk20a.h ] ptimer: safe: no diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index b7a3c9d39..3a84e2c02 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -920,7 +920,6 @@ nvgpu-y += \ hal/fb/intr/fb_intr_ecc_ga10b_fusa.o \ hal/fb/vab/vab_ga10b.o \ hal/priv_ring/priv_ring_ga10b_fusa.o \ - hal/ptimer/ptimer_ga10b_fusa.o \ hal/perf/perf_ga10b.o \ hal/regops/regops_ga10b.o \ hal/regops/allowlist_ga10b.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 5fe179f40..ba8d107b9 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -821,7 +821,6 @@ srcs += hal/init/hal_ga10b.c \ hal/fb/intr/fb_intr_ga10b_fusa.c \ hal/fb/intr/fb_intr_ecc_ga10b_fusa.c \ hal/priv_ring/priv_ring_ga10b_fusa.c \ - hal/ptimer/ptimer_ga10b_fusa.c \ hal/power_features/cg/ga10b_gating_reglist.c \ hal/therm/therm_ga10b_fusa.c \ hal/ce/ce_ga10b_fusa.c \ diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index c08b55bbe..2caa1d381 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -148,7 +148,6 @@ #include "hal/ptimer/ptimer_gk20a.h" #include "hal/ptimer/ptimer_gp10b.h" #include "hal/ptimer/ptimer_gv11b.h" -#include "hal/ptimer/ptimer_ga10b.h" #ifdef CONFIG_NVGPU_DEBUGGER #include "hal/regops/regops_ga100.h" #include "hal/regops/allowlist_ga100.h" diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index b7bb4b958..7fe4196f0 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -118,7 +118,6 @@ #include "hal/ptimer/ptimer_gk20a.h" #include "hal/ptimer/ptimer_gp10b.h" #include "hal/ptimer/ptimer_gv11b.h" -#include "hal/ptimer/ptimer_ga10b.h" #ifdef CONFIG_NVGPU_DEBUGGER #include "hal/regops/regops_ga10b.h" #include "hal/regops/allowlist_ga10b.h" @@ -1556,7 +1555,7 @@ static const struct gops_bus ga10b_ops_bus = { }; static const struct gops_ptimer ga10b_ops_ptimer = { - .isr = ga10b_ptimer_isr, + .isr = gk20a_ptimer_isr, #ifdef CONFIG_NVGPU_IOCTL_NON_FUSA .read_ptimer = gk20a_read_ptimer, .get_timestamps_zipper = nvgpu_get_timestamps_zipper, diff --git a/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b.h b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b.h index e1380563b..e0f20a968 100644 --- a/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b.h +++ b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,6 +23,36 @@ #define NVGPU_PRIV_RING_GA10B_H #include +#include + +/* + * Helper macros for decoding host pri error of pattern: + * BAD001xx - HOST_PRI_TIMEOUT. + * BAD002xx - HOST_PRI_DECODE. + * BAD0DAxx - HOST_PRI_SQUASH. + * Where xx is interpreted as follows: + * bits [7:0] = subid. + */ +#define HOST_PRIV_SUBID_MSK_VAL(x) \ + ((x) & (nvgpu_safe_sub_u32(BIT32(8U), 1U))) + +/* + * Helper macros for decoding fecs pri floorsweep error of pattern: + * BADF13xx - FECS_PRI_FLOORSWEEP. + * Where xx is interpreted as follows: + * bits [4:0] = source id. + */ +#define FECS_PRIV_SOURCEID_MSK_VAL(x) \ + ((x) & (nvgpu_safe_sub_u32(BIT32(5U), 1U))) + +/* + * Helper macros for decoding fecs pri orphan error of pattern: + * BADF20xx - FECS_PRI_FLOORSWEEP. + * Where xx is interpreted as follows: + * bits [7:0] = target ringstation. + */ +#define FECS_PRIV_ORPHAN_TARGET_RINGSTN_MSK_VAL(x) \ + ((x) & (nvgpu_safe_sub_u32(BIT32(8U), 1U))) /* * Helper macros for decoding falcon mem access violation of pattern: @@ -33,7 +63,8 @@ * bits [5:4] = access level. * bits [3:0] = existing priv level mask. */ -#define FALCON_DMEM_VIOLATION_MSK() BIT32(7U) +#define FALCON_DMEM_VIOLATION_MSK() BIT32(7U) +#define FALCON_MEM_VIOLATION_MSK_VIOLATION() BIT32(6U) #define FALCON_MEM_VIOLATION_PRIVLEVEL_ACCESS_VAL(x) \ (((x) & (BIT32(5U) | BIT32(4U))) >> 4U) #define FALCON_MEM_VIOLATION_PRIVLEVEL_MSK_VAL(x) \ @@ -58,7 +89,7 @@ /* * Helper macros for decoding PRI access violation error of pattern: - * BADF51xx, BADF52xx - direct/indirect PRIV_LEVEL_VIOLATION. + * BADF51xx - direct PRIV_LEVEL_VIOLATION. * Where xx is interpreted as follows: * bits [7:6] = b'00 * bits [5:4] = request_priv_level @@ -69,6 +100,20 @@ #define PRI_ACCESS_VIOLATON_LEVEL_VAL(x) \ (((x) & (BIT32(5U) | BIT32(4U))) >> 4U) +/* + * Helper macros for decoding PRI access violation error of pattern: + * BADF52xx - indirect PRIV_LEVEL_VIOLATION. + * Where xx is interpreted as follows: + * bits [7:6] = b'00 + * bits [5:4] = current_request_priv_level + * bits [3:2] = b'00 + * bits [1:0] = orig_request_priv_level + */ +#define PRI_ACCESS_VIOLATION_CUR_REQPL_VAL(x) \ + (((x) & (BIT32(5U) | BIT32(4U))) >> 4U) +#define PRI_ACCESS_VIOLATION_ORIG_REQPL_VAL(x) \ + ((x) & (BIT32(1U) | BIT32(0U))) + /* * Helper macros for decoding source enable violations of pattern: * BADF57xx and BADF59xx - direct/indirect SOURCE_ENABLE_VIOLATION. @@ -83,6 +128,25 @@ #define SRC_EN_VIOLATION_SRCID_VAL(x) \ ((x) & (BIT32(4U) | BIT32(3U) | BIT32(2U) | BIT32(1U) | BIT32(0U))) +/* + * Helper macros for decoding pri lock from security sensor of pattern: + * BADF60xx - pri lock due to security sensor. + * Where xx is interpreted as follows: + * bits [7:6] = b'00 + * bits [5] = pmu_dcls + * bits [4] = gsp_dcls + * bits [3] = sec2_dcls + * bits [2] = nvdclk_scpm + * bits [1] = fuse_scm + * bits [0] = fuse_prod + */ +#define PRI_LOCK_SEC_SENSOR_PMU_MSK() BIT32(5U) +#define PRI_LOCK_SEC_SENSOR_GSP_MSK() BIT32(4U) +#define PRI_LOCK_SEC_SENSOR_SEC2_MSK() BIT32(3U) +#define PRI_LOCK_SEC_SENSOR_NVDCLK_MSK() BIT32(2U) +#define PRI_LOCK_SEC_SENSOR_FUSE_SCM_MSK() BIT32(1U) +#define PRI_LOCK_SEC_SENSOR_FUSE_PROD_MSK() BIT32(0U) + /* * Helper macros for decoding local priv ring errors of pattern: * BADF53xx - LOCAL_PRIV_RING_ERR diff --git a/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b_fusa.c index 0d5e1cd95..066a48076 100644 --- a/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_ga10b_fusa.c @@ -63,12 +63,20 @@ */ static void decode_pri_client_error(struct gk20a *g, u32 value); static void decode_pri_local_error(struct gk20a *g, u32 value); -static void decode_pri_access_violation(struct gk20a *g, u32 value); static void decode_pri_falcom_mem_violation(struct gk20a *g, u32 value); static void decode_pri_route_error(struct gk20a *g, u32 value); static void decode_pri_source_en_violation(struct gk20a *g, u32 value); static void decode_pri_target_mask_violation(struct gk20a *g, u32 value); static void decode_pri_undefined_error_extra_info(struct gk20a *g, u32 value); +static void decode_host_pri_error(struct gk20a *g, u32 value); +static void decode_fecs_floorsweep_error(struct gk20a *g, u32 value); +static void decode_gcgpc_error(struct gk20a *g, u32 value); +static void decode_pri_local_decode_error(struct gk20a *g, u32 value); +static void decode_pri_client_badf50_error(struct gk20a *g, u32 value); +static void decode_fecs_pri_orphan_error(struct gk20a *g, u32 value); +static void decode_pri_direct_access_violation(struct gk20a *g, u32 value); +static void decode_pri_indirect_access_violation(struct gk20a *g, u32 value); +static void decode_pri_lock_sec_sensor_violation(struct gk20a *g, u32 value); /* * Helper functions to handle priv_ring bits associated with status0. @@ -86,10 +94,11 @@ struct pri_error_code { }; /* - * Group pri error codes in the range [0xbadf001xx - 0xbadf001xx]. + * Group pri error codes in the range [0xbad001xx - 0xbad002xx]. */ static struct pri_error_code bad001xx[] = { - { "host pri timeout error", decode_pri_client_error }, + { "host pri timeout error", decode_host_pri_error }, + { "host pri decode error", decode_host_pri_error }, { "undefined", decode_pri_undefined_error_extra_info } }; static const size_t nbad001xx_entries = sizeof(bad001xx) / sizeof(*bad001xx); @@ -117,9 +126,9 @@ static const size_t nbad0b0xx_entries = sizeof(bad0b0xx) / sizeof(*bad0b0xx); */ static struct pri_error_code badf1yxx[] = { { "client timeout", decode_pri_client_error }, - { "decode error", decode_pri_client_error }, + { "decode error (range not found)", decode_pri_undefined_error_extra_info }, { "client in reset", decode_pri_client_error }, - { "client floorswept", decode_pri_client_error }, + { "client floorswept", decode_fecs_floorsweep_error }, { "client stuck ack", decode_pri_client_error }, { "client expected ack", decode_pri_client_error }, { "fence error", decode_pri_client_error }, @@ -134,10 +143,15 @@ static const size_t nbadf1yxx_entries = sizeof(badf1yxx) / sizeof(*badf1yxx); * Group pri error codes in the range [0xbadf20xx - 0xbadf23xx]. */ static struct pri_error_code badf2yxx[] = { - { "orphan(gpc/fbp)", decode_pri_client_error }, - { "power ok timeout", decode_pri_client_error }, - { "orphan(gpc/fbp) powergated", decode_pri_client_error }, + { "orphan(gpc/fbp)", decode_fecs_pri_orphan_error }, + { "power ok timeout", decode_pri_local_error }, + { "orphan(gpc/fbp) powergated", decode_fecs_pri_orphan_error }, { "target powergated", decode_pri_client_error }, + { "orphan gcgpc", decode_gcgpc_error }, + { "decode gcgpc", decode_gcgpc_error }, + { "local priv decode error", decode_pri_local_decode_error }, + { "priv poisoned", decode_pri_client_error }, + { "trans type", decode_pri_client_error }, { "undefined", decode_pri_undefined_error_extra_info } }; static const size_t nbadf2yxx_entries = sizeof(badf2yxx) / sizeof(*badf2yxx); @@ -166,9 +180,9 @@ static const size_t nbadf4yxx_entries = sizeof(badf4yxx) / sizeof(*badf4yxx); * Group pri error codes in the range [0xbadf50xx - 0xbadf59xx]. */ static struct pri_error_code badf5yxx[] = { - { "client error", decode_pri_client_error }, - { "priv level violation", decode_pri_access_violation }, - { "indirect priv level violation", decode_pri_access_violation }, + { "client error", decode_pri_client_badf50_error }, + { "priv level violation", decode_pri_direct_access_violation }, + { "indirect priv level violation", decode_pri_indirect_access_violation }, { "local priv ring error", decode_pri_local_error }, { "falcon mem priv level violation", decode_pri_falcom_mem_violation }, { "route error", decode_pri_route_error }, @@ -184,7 +198,7 @@ static const size_t nbadf5yxx_entries = sizeof(badf5yxx) / sizeof(*badf5yxx); * Group pri error codes in the range [0xbadf60xx]. */ static struct pri_error_code badf6yxx[] = { - { "lock from security sensor", decode_pri_undefined_error_extra_info }, + { "lock from security sensor", decode_pri_lock_sec_sensor_violation }, { "undefined", decode_pri_undefined_error_extra_info } }; static const size_t nbadf6yxx_entries = sizeof(badf6yxx) / sizeof(*badf6yxx); @@ -219,6 +233,7 @@ sizeof(pri_client_error_extra_2x) / sizeof(*pri_client_error_extra_2x); */ static const char *pri_client_error_extra_4x[] = { "no such address", + "task protection", "external error", "index range errror", "reset", @@ -247,18 +262,49 @@ static void decode_pri_undefined_error_extra_info(struct gk20a *g, u32 value) nvgpu_err(g, "[Extra Info]: undefined, value(0x%x)", value); } +static void decode_host_pri_error(struct gk20a *g, u32 value) +{ + u32 sub_id; + + sub_id = HOST_PRIV_SUBID_MSK_VAL(value); + + nvgpu_err(g, "[Extra Info]: sub_id(0x%x)", sub_id); +} + +static void decode_fecs_floorsweep_error(struct gk20a *g, u32 value) +{ + u32 source_id; + + source_id = FECS_PRIV_SOURCEID_MSK_VAL(value); + + nvgpu_err(g, "[Extra Info]: client floorswept source_id(0x%x)", source_id); +} + +static void decode_gcgpc_error(struct gk20a *g, u32 value) +{ + u32 source_id; + + source_id = FECS_PRIV_SOURCEID_MSK_VAL(value); + + nvgpu_err(g, "[Extra Info]: GCGPC error source_id(0x%x)", source_id); +} + +static void decode_pri_local_decode_error(struct gk20a *g, u32 value) +{ + u32 source_id; + + source_id = FECS_PRIV_SOURCEID_MSK_VAL(value); + + nvgpu_err(g, "[Extra Info]: pri local decode source_id(0x%x)", source_id); +} + static void decode_pri_client_error(struct gk20a *g, u32 value) { const char **lookup_table = { (const char* []){ "undefined" } }; size_t lookup_table_size = 1; size_t index = 0; - if (value >= pri_sys_pri_error_extra_no_such_address_v()) { - index = value - pri_sys_pri_error_extra_no_such_address_v(); - lookup_table = pri_client_error_extra_4x; - lookup_table_size = npri_client_error_extra_4x; - - } else if (value >= pri_sys_pri_error_extra_extra_sync_req_v()) { + if (value >= pri_sys_pri_error_extra_extra_sync_req_v()) { index = value - pri_sys_pri_error_extra_extra_sync_req_v(); lookup_table = pri_client_error_extra_2x; lookup_table_size = npri_client_error_extra_2x; @@ -282,6 +328,42 @@ static void decode_pri_client_error(struct gk20a *g, u32 value) lookup_table[index], value); } +static void decode_pri_client_badf50_error(struct gk20a *g, u32 value) +{ + const char **lookup_table = { (const char* []){ "undefined" } }; + size_t lookup_table_size = 1; + size_t index = 0; + + if (value >= pri_sys_pri_error_extra_no_such_address_v()) { + index = (size_t)value - pri_sys_pri_error_extra_no_such_address_v(); + lookup_table = pri_client_error_extra_4x; + lookup_table_size = npri_client_error_extra_4x; + + } + + /* + * An index which falls outside the lookup table size is considered + * unknown. The index is updated to the last valid entry of the table, + * which is reserved for this purpose. + */ + if (index >= lookup_table_size) { + index = lookup_table_size - 1UL; + } + + nvgpu_err(g, "[Extra Info]: %s, value(0x%x)", + lookup_table[index], value); +} + +static void decode_fecs_pri_orphan_error(struct gk20a *g, u32 value) +{ + u32 target_ringstation; + + target_ringstation = FECS_PRIV_ORPHAN_TARGET_RINGSTN_MSK_VAL(value); + + nvgpu_err(g, "[Extra Info]: target_ringstation(0x%x)", + target_ringstation); +} + static void decode_pri_target_mask_violation(struct gk20a *g, u32 value) { u32 target_mask, source_id; @@ -293,7 +375,7 @@ static void decode_pri_target_mask_violation(struct gk20a *g, u32 value) target_mask, source_id); } -static void decode_pri_access_violation(struct gk20a *g, u32 value) +static void decode_pri_direct_access_violation(struct gk20a *g, u32 value) { u32 priv_mask = PRI_ACCESS_VIOLATION_MSK_VAL(value); u32 priv_level = PRI_ACCESS_VIOLATON_LEVEL_VAL(value); @@ -302,6 +384,15 @@ static void decode_pri_access_violation(struct gk20a *g, u32 value) priv_level, priv_mask); } +static void decode_pri_indirect_access_violation(struct gk20a *g, u32 value) +{ + u32 cur_priv_level = PRI_ACCESS_VIOLATION_CUR_REQPL_VAL(value); + u32 orig_priv_level = PRI_ACCESS_VIOLATION_ORIG_REQPL_VAL(value); + + nvgpu_err(g, "[Extra Info]: orig_priv_level(0x%x), cur_priv_level(0x%x)", + orig_priv_level, cur_priv_level); +} + static void decode_pri_falcom_mem_violation(struct gk20a *g, u32 value) { bool imem_violation = true; @@ -313,9 +404,11 @@ static void decode_pri_falcom_mem_violation(struct gk20a *g, u32 value) } fault_priv_level = FALCON_MEM_VIOLATION_PRIVLEVEL_ACCESS_VAL(value); mem_priv_level_mask = FALCON_MEM_VIOLATION_PRIVLEVEL_MSK_VAL(value); - nvgpu_err(g, "[Extra Info]: %s violation, fault_priv_level(0x%x),"\ + nvgpu_err(g, "[Extra Info]: %s violation %s, fault_priv_level(0x%x),"\ "mem_priv_level_mask(0x%x)", imem_violation ? "IMEM" : "DMEM", + (value & FALCON_MEM_VIOLATION_MSK_VIOLATION()) != 0U ? + "unequal" : "mask violation", fault_priv_level, mem_priv_level_mask); } @@ -368,6 +461,18 @@ static void decode_pri_local_error(struct gk20a *g, u32 value) PRIV_LOCAL_TARGET_INDEX(value)); } +static void decode_pri_lock_sec_sensor_violation(struct gk20a *g, u32 value) +{ + nvgpu_err(g, "[Extra Info]: pmu(%s), gsp(%s),"\ + " sec2(%s), nvdclk(%s), fuse_scm(%s), fuse_prod(%s)", + (value & PRI_LOCK_SEC_SENSOR_PMU_MSK()) != 0U ? "yes" : "no", + (value & PRI_LOCK_SEC_SENSOR_GSP_MSK()) != 0U ? "yes" : "no", + (value & PRI_LOCK_SEC_SENSOR_SEC2_MSK()) != 0U ? "yes" : "no", + (value & PRI_LOCK_SEC_SENSOR_NVDCLK_MSK()) != 0U ? "yes" : "no", + (value & PRI_LOCK_SEC_SENSOR_FUSE_SCM_MSK()) != 0U ? "yes" : "no", + (value & PRI_LOCK_SEC_SENSOR_FUSE_PROD_MSK()) != 0U ? "yes" : "no"); +} + void ga10b_priv_ring_decode_error_code(struct gk20a *g, u32 error_code) { u32 err_code; @@ -378,12 +483,17 @@ void ga10b_priv_ring_decode_error_code(struct gk20a *g, u32 error_code) size_t lookup_table_size = 1; size_t index = 0; - nvgpu_report_err_to_sdl(g, NVGPU_ERR_MODULE_PRI, - GPU_PRI_ACCESS_VIOLATION); - err_code = pri_sys_pri_error_code_v(error_code); error_extra = pri_sys_pri_error_extra_v(error_code); + if (err_code == pri_sys_pri_error_code_fecs_pri_timeout_v()) { + nvgpu_report_err_to_sdl(g, NVGPU_ERR_MODULE_PRI, + GPU_PRI_TIMEOUT_ERROR); + } else { + nvgpu_report_err_to_sdl(g, NVGPU_ERR_MODULE_PRI, + GPU_PRI_ACCESS_VIOLATION); + } + if (err_code >= pri_sys_pri_error_code_fecs_pri_lock_from_security_sensor_v()) { index = err_code - pri_sys_pri_error_code_fecs_pri_lock_from_security_sensor_v(); diff --git a/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b_fusa.c index 1ad0991e4..d65b337c4 100644 --- a/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b_fusa.c @@ -71,9 +71,6 @@ void gp10b_priv_ring_decode_error_code(struct gk20a *g, { u32 error_type_index; - nvgpu_report_err_to_sdl(g, NVGPU_ERR_MODULE_PRI, - GPU_PRI_ACCESS_VIOLATION); - error_type_index = (error_code & 0x00000f00U) >> 8U; error_code = error_code & 0xBADFf000U; diff --git a/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b.h b/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b.h deleted file mode 100644 index 8f6604b37..000000000 --- a/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef PTIMER_GA10B_H -#define PTIMER_GA10B_H - -#include - -struct gk20a; - -void ga10b_ptimer_isr(struct gk20a *g); - -#endif /* PTIMER_GA10B_H */ diff --git a/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b_fusa.c deleted file mode 100644 index 41a615cb5..000000000 --- a/drivers/gpu/nvgpu/hal/ptimer/ptimer_ga10b_fusa.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include - -#include "ptimer_ga10b.h" - -#include - -void ga10b_ptimer_isr(struct gk20a *g) -{ - u32 save0, save1, fecs_errcode = 0; - u32 error_addr; - - save0 = nvgpu_readl(g, timer_pri_timeout_save_0_r()); - if (timer_pri_timeout_save_0_fecs_tgt_v(save0) != 0U) { - /* - * write & addr fields in timeout_save0 - * might not be reliable - */ - fecs_errcode = nvgpu_readl(g, - timer_pri_timeout_fecs_errcode_r()); - } - - save1 = nvgpu_readl(g, timer_pri_timeout_save_1_r()); - error_addr = timer_pri_timeout_save_0_addr_v(save0) << 2; - nvgpu_err(g, "PRI timeout: ADR 0x%08x " - "%s DATA 0x%08x", - error_addr, - (timer_pri_timeout_save_0_write_v(save0) != 0U) ? - "WRITE" : "READ", save1); - - nvgpu_writel(g, timer_pri_timeout_save_0_r(), 0); - nvgpu_writel(g, timer_pri_timeout_save_1_r(), 0); - - if (fecs_errcode != 0U) { - nvgpu_err(g, "FECS_ERRCODE 0x%08x", fecs_errcode); - if (g->ops.priv_ring.decode_error_code != NULL) { - g->ops.priv_ring.decode_error_code(g, - fecs_errcode); - } - } - - nvgpu_report_err_to_sdl(g, NVGPU_ERR_MODULE_PRI, - GPU_PRI_TIMEOUT_ERROR); -} diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c index 87f6ece68..e0715ba80 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c @@ -63,7 +63,6 @@ #include "hal/netlist/netlist_gv11b.h" #include "hal/netlist/netlist_ga10b.h" #include "hal/ptimer/ptimer_gv11b.h" -#include "hal/ptimer/ptimer_ga10b.h" #ifdef CONFIG_NVGPU_DEBUGGER #include "hal/regops/regops_ga10b.h" #include "hal/regops/allowlist_ga10b.h"