diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
index 1d3285d7f..3f2a9e96d 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c
@@ -31,6 +31,12 @@
 #include <nvgpu/boardobj.h>
 #include <nvgpu/boardobjgrp.h>
 
+#include "clk/clk.h"
+#include "clk/clk_vin.h"
+#include "clk/clk_fll.h"
+#include "volt/volt.h"
+#include "pstate/pstate.h"
+
 /* PMU NS UCODE IMG */
 #define NVGPU_PMU_NS_UCODE_IMAGE	"gpmu_ucode.bin"
 
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index b3347e958..12e0008bf 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -50,6 +50,7 @@
 #include "common/pmu/pmu_gp106.h"
 #include "common/pmu/acr_gm20b.h"
 #include "common/pmu/acr_gp106.h"
+#include "pmu_perf/pmu_perf.h"
 
 #include "gk20a/fifo_gk20a.h"
 #include "gk20a/fecs_trace_gk20a.h"
diff --git a/drivers/gpu/nvgpu/gp106/mclk_gp106.c b/drivers/gpu/nvgpu/gp106/mclk_gp106.c
index 711285627..d0b731b49 100644
--- a/drivers/gpu/nvgpu/gp106/mclk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/mclk_gp106.c
@@ -33,6 +33,7 @@
 #include <linux/debugfs.h>
 #include "os/linux/os_linux.h"
 #endif
+#include "pstate/pstate.h"
 #include "gp106/mclk_gp106.h"
 
 #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index fb8cde1ae..07743db43 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -51,6 +51,10 @@ struct nvgpu_gpu_ctxsw_trace_filter;
 struct priv_cmd_entry;
 struct nvgpu_setup_bind_args;
 struct clk_pmupstate;
+struct perf_pmupstate;
+struct vin_device_v20;
+struct avfsvinobjs;
+struct set_fll_clk;
 
 #include <nvgpu/lock.h>
 #include <nvgpu/thread.h>
@@ -75,7 +79,6 @@ struct clk_pmupstate;
 #include "gk20a/clk_gk20a.h"
 #include "gk20a/fifo_gk20a.h"
 #include "gk20a/gr_gk20a.h"
-#include "pmu_perf/pmu_perf.h"
 #include "pmgr/pmgr.h"
 #include "therm/thrm.h"
 
@@ -1491,7 +1494,7 @@ struct gk20a {
 	struct nvgpu_acr acr;
 	struct nvgpu_ecc ecc;
 	struct clk_pmupstate *clk_pmu;
-	struct perf_pmupstate perf_pmu;
+	struct perf_pmupstate *perf_pmu;
 	struct pmgr_pmupstate pmgr_pmu;
 	struct therm_pmupstate therm_pmu;
 	struct nvgpu_sec2 sec2;
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c
index 303eb785c..74271a16c 100644
--- a/drivers/gpu/nvgpu/lpwr/lpwr.c
+++ b/drivers/gpu/nvgpu/lpwr/lpwr.c
@@ -37,7 +37,7 @@ static int get_lpwr_idx_table(struct gk20a *g)
 	u8 *entry_addr;
 	u32 idx;
 	struct nvgpu_lpwr_bios_idx_data *pidx_data =
-			&g->perf_pmu.lpwr.lwpr_bios_data.idx;
+			&g->perf_pmu->lpwr.lwpr_bios_data.idx;
 	struct nvgpu_bios_lpwr_idx_table_1x_header header = { 0 };
 	struct nvgpu_bios_lpwr_idx_table_1x_entry entry = { 0 };
 
@@ -81,7 +81,7 @@ static int get_lpwr_gr_table(struct gk20a *g)
 	u8 *entry_addr;
 	u32 idx;
 	struct nvgpu_lpwr_bios_gr_data *pgr_data =
-			&g->perf_pmu.lpwr.lwpr_bios_data.gr;
+			&g->perf_pmu->lpwr.lwpr_bios_data.gr;
 	struct nvgpu_bios_lpwr_gr_table_1x_header header = { 0 };
 	struct nvgpu_bios_lpwr_gr_table_1x_entry entry = { 0 };
 
@@ -127,7 +127,7 @@ static int get_lpwr_ms_table(struct gk20a *g)
 	u8 *entry_addr;
 	u32 idx;
 	struct nvgpu_lpwr_bios_ms_data *pms_data =
-			&g->perf_pmu.lpwr.lwpr_bios_data.ms;
+			&g->perf_pmu->lpwr.lwpr_bios_data.ms;
 	struct nvgpu_bios_lpwr_ms_table_1x_header header = { 0 };
 	struct nvgpu_bios_lpwr_ms_table_1x_entry entry = { 0 };
 
@@ -254,8 +254,8 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
 			NV_PMU_PG_PARAM_MCLK_CHANGE_GDDR5_WR_TRAINING_ENABLED;
 	}
 
-	if (payload != g->perf_pmu.lpwr.mclk_change_cache) {
-		g->perf_pmu.lpwr.mclk_change_cache = payload;
+	if (payload != g->perf_pmu->lpwr.mclk_change_cache) {
+		g->perf_pmu->lpwr.mclk_change_cache = payload;
 
 		cmd.hdr.unit_id = PMU_UNIT_PG;
 		cmd.hdr.size = PMU_CMD_HDR_SIZE +
@@ -317,9 +317,9 @@ u32 nvgpu_lpwr_post_init(struct gk20a *g)
 bool nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num)
 {
 	struct nvgpu_lpwr_bios_ms_data *pms_data =
-			&g->perf_pmu.lpwr.lwpr_bios_data.ms;
+			&g->perf_pmu->lpwr.lwpr_bios_data.ms;
 	struct nvgpu_lpwr_bios_idx_data *pidx_data =
-			&g->perf_pmu.lpwr.lwpr_bios_data.idx;
+			&g->perf_pmu->lpwr.lwpr_bios_data.idx;
 	struct pstate *pstate = pstate_find(g, pstate_num);
 	u32 ms_idx;
 
@@ -340,9 +340,9 @@ bool nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num)
 bool nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num)
 {
 	struct nvgpu_lpwr_bios_gr_data *pgr_data =
-			&g->perf_pmu.lpwr.lwpr_bios_data.gr;
+			&g->perf_pmu->lpwr.lwpr_bios_data.gr;
 	struct nvgpu_lpwr_bios_idx_data *pidx_data =
-			&g->perf_pmu.lpwr.lwpr_bios_data.idx;
+			&g->perf_pmu->lpwr.lwpr_bios_data.idx;
 	struct pstate *pstate = pstate_find(g, pstate_num);
 	u32 idx;
 
diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.h b/drivers/gpu/nvgpu/pmgr/pwrdev.h
index 8065adc39..2512e29f9 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrdev.h
+++ b/drivers/gpu/nvgpu/pmgr/pwrdev.h
@@ -25,6 +25,7 @@
 #define NVGPU_PMGR_PWRDEV_H
 
 #include <nvgpu/boardobj.h>
+#include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
 #include <nvgpu/pmuif/ctrlpmgr.h>
 
diff --git a/drivers/gpu/nvgpu/pmu_perf/perf_gv100.c b/drivers/gpu/nvgpu/pmu_perf/perf_gv100.c
index 45f7ab6b4..3d0d4f60e 100644
--- a/drivers/gpu/nvgpu/pmu_perf/perf_gv100.c
+++ b/drivers/gpu/nvgpu/pmu_perf/perf_gv100.c
@@ -27,13 +27,14 @@
 #include <nvgpu/gk20a.h>
 
 #include "perf_gv100.h"
+#include "pmu_perf/pmu_perf.h"
 
 static int pmu_set_boot_clk_runcb_fn(void *arg)
 {
 	struct gk20a *g = (struct gk20a *)arg;
 	struct nvgpu_pmu *pmu = &g->pmu;
 	struct nv_pmu_rpc_struct_perf_load rpc;
-	struct perf_pmupstate *perf_pmu = &g->perf_pmu;
+	struct perf_pmupstate *perf_pmu = g->perf_pmu;
 	struct nvgpu_vfe_invalidate *vfe_init = &perf_pmu->vfe_init;
 	int status = 0;
 
@@ -61,7 +62,7 @@ static int pmu_set_boot_clk_runcb_fn(void *arg)
 static int gv100_pmu_handle_perf_event(struct gk20a *g, void *pmumsg)
 {
 	struct nv_pmu_perf_msg *msg = (struct nv_pmu_perf_msg *)pmumsg;
-	struct perf_pmupstate *perf_pmu = &g->perf_pmu;
+	struct perf_pmupstate *perf_pmu = g->perf_pmu;
 
 	nvgpu_log_fn(g, " ");
 	switch (msg->msg_type) {
@@ -78,7 +79,7 @@ static int gv100_pmu_handle_perf_event(struct gk20a *g, void *pmumsg)
 
 u32 perf_pmu_init_vfe_perf_event(struct gk20a *g)
 {
-	struct perf_pmupstate *perf_pmu = &g->perf_pmu;
+	struct perf_pmupstate *perf_pmu = g->perf_pmu;
 	char thread_name[64];
 	u32 err = 0;
 
diff --git a/drivers/gpu/nvgpu/pmu_perf/pmu_perf.c b/drivers/gpu/nvgpu/pmu_perf/pmu_perf.c
index 40d85b21f..4cf759312 100644
--- a/drivers/gpu/nvgpu/pmu_perf/pmu_perf.c
+++ b/drivers/gpu/nvgpu/pmu_perf/pmu_perf.c
@@ -127,3 +127,23 @@ int perf_pmu_vfe_load(struct gk20a *g)
 done:
 	return status;
 }
+
+int perf_pmu_init_pmupstate(struct gk20a *g)
+{
+	/* If already allocated, do not re-allocate */
+	if (g->perf_pmu != NULL) {
+		return 0;
+	}
+
+	g->perf_pmu = nvgpu_kzalloc(g, sizeof(*g->perf_pmu));
+	if (g->perf_pmu == NULL) {
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+void perf_pmu_free_pmupstate(struct gk20a *g)
+{
+	nvgpu_kfree(g, g->perf_pmu);
+}
diff --git a/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h b/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h
index c4ee43d7a..c66c53946 100644
--- a/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h
+++ b/drivers/gpu/nvgpu/pmu_perf/pmu_perf.h
@@ -79,6 +79,8 @@ struct perf_pmupstate {
 	struct nvgpu_vfe_invalidate vfe_init;
 };
 
+int perf_pmu_init_pmupstate(struct gk20a *g);
+void perf_pmu_free_pmupstate(struct gk20a *g);
 int perf_pmu_vfe_load(struct gk20a *g);
 
 #endif /* NVGPU_PERF_H */
diff --git a/drivers/gpu/nvgpu/pmu_perf/vfe_equ.c b/drivers/gpu/nvgpu/pmu_perf/vfe_equ.c
index d4767ce81..3a5075172 100644
--- a/drivers/gpu/nvgpu/pmu_perf/vfe_equ.c
+++ b/drivers/gpu/nvgpu/pmu_perf/vfe_equ.c
@@ -81,7 +81,7 @@ int vfe_equ_sw_setup(struct gk20a *g)
 
 	nvgpu_log_info(g, " ");
 
-	status = boardobjgrpconstruct_e255(g, &g->perf_pmu.vfe_equobjs.super);
+	status = boardobjgrpconstruct_e255(g, &g->perf_pmu->vfe_equobjs.super);
 	if (status != 0) {
 		nvgpu_err(g,
 			  "error creating boardobjgrp for clk domain, status - 0x%x",
@@ -89,8 +89,8 @@ int vfe_equ_sw_setup(struct gk20a *g)
 		goto done;
 	}
 
-	pboardobjgrp = &g->perf_pmu.vfe_equobjs.super.super;
-	pvfeequobjs = &(g->perf_pmu.vfe_equobjs);
+	pboardobjgrp = &g->perf_pmu->vfe_equobjs.super.super;
+	pvfeequobjs = &(g->perf_pmu->vfe_equobjs);
 
 	BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, PERF, VFE_EQU);
 
@@ -123,7 +123,7 @@ int vfe_equ_pmu_setup(struct gk20a *g)
 
 	nvgpu_log_info(g, " ");
 
-	pboardobjgrp = &g->perf_pmu.vfe_equobjs.super.super;
+	pboardobjgrp = &g->perf_pmu->vfe_equobjs.super.super;
 
 	if (!pboardobjgrp->bconstructed) {
 		return -EINVAL;
diff --git a/drivers/gpu/nvgpu/pmu_perf/vfe_var.c b/drivers/gpu/nvgpu/pmu_perf/vfe_var.c
index 3a9ab2955..c0a463e83 100644
--- a/drivers/gpu/nvgpu/pmu_perf/vfe_var.c
+++ b/drivers/gpu/nvgpu/pmu_perf/vfe_var.c
@@ -110,7 +110,7 @@ int vfe_var_sw_setup(struct gk20a *g)
 
 	nvgpu_log_info(g, " ");
 
-	status = boardobjgrpconstruct_e32(g, &g->perf_pmu.vfe_varobjs.super);
+	status = boardobjgrpconstruct_e32(g, &g->perf_pmu->vfe_varobjs.super);
 	if (status != 0) {
 		nvgpu_err(g,
 			  "error creating boardobjgrp for clk domain, status - 0x%x",
@@ -118,8 +118,8 @@ int vfe_var_sw_setup(struct gk20a *g)
 		goto done;
 	}
 
-	pboardobjgrp = &g->perf_pmu.vfe_varobjs.super.super;
-	pvfevarobjs = &g->perf_pmu.vfe_varobjs;
+	pboardobjgrp = &g->perf_pmu->vfe_varobjs.super.super;
+	pvfevarobjs = &g->perf_pmu->vfe_varobjs;
 
 	BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, PERF, VFE_VAR);
 
@@ -142,7 +142,7 @@ int vfe_var_sw_setup(struct gk20a *g)
 	}
 
 	status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
-				&g->perf_pmu.vfe_varobjs.super.super,
+				&g->perf_pmu->vfe_varobjs.super.super,
 				perf, PERF, vfe_var, VFE_VAR);
 	if (status != 0) {
 		nvgpu_err(g,
@@ -163,7 +163,7 @@ int vfe_var_pmu_setup(struct gk20a *g)
 
 	nvgpu_log_info(g, " ");
 
-	pboardobjgrp = &g->perf_pmu.vfe_varobjs.super.super;
+	pboardobjgrp = &g->perf_pmu->vfe_varobjs.super.super;
 
 	if (!pboardobjgrp->bconstructed) {
 		return -EINVAL;
diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c
index 3ab68d507..db2c68d17 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.c
+++ b/drivers/gpu/nvgpu/pstate/pstate.c
@@ -36,13 +36,14 @@ static int pstate_sw_setup(struct gk20a *g);
 
 void gk20a_deinit_pstate_support(struct gk20a *g)
 {
+	perf_pmu_free_pmupstate(g);
 	clk_free_pmupstate(g);
 
 	if (g->ops.clk.mclk_deinit != NULL) {
 		g->ops.clk.mclk_deinit(g);
 	}
 
-	nvgpu_mutex_destroy(&g->perf_pmu.pstatesobjs.pstate_mutex);
+	nvgpu_mutex_destroy(&g->perf_pmu->pstatesobjs.pstate_mutex);
 }
 
 /*sw setup for pstate components*/
@@ -57,89 +58,96 @@ int gk20a_init_pstate_support(struct gk20a *g)
 		return err;
 	}
 
-	err = volt_rail_sw_setup(g);
+	err = perf_pmu_init_pmupstate(g);
 	if (err != 0) {
 		goto err_clk_init_pmupstate;
 	}
 
+	err = volt_rail_sw_setup(g);
+	if (err != 0) {
+		goto err_perf_pmu_init_pmupstate;
+	}
+
 	err = volt_dev_sw_setup(g);
 	if (err != 0) {
-		goto err_clk_init_pmupstate;
+		goto err_perf_pmu_init_pmupstate;
 	}
 
 	err = volt_policy_sw_setup(g);
 	if (err != 0) {
-		goto err_clk_init_pmupstate;
+		goto err_perf_pmu_init_pmupstate;
 	}
 
 	err = clk_vin_sw_setup(g);
 	if (err != 0) {
-		goto err_clk_init_pmupstate;
+		goto err_perf_pmu_init_pmupstate;
 	}
 
 	err = clk_fll_sw_setup(g);
 	if (err != 0) {
-		goto err_clk_init_pmupstate;
+		goto err_perf_pmu_init_pmupstate;
 	}
 
 	err = therm_domain_sw_setup(g);
 	if (err != 0) {
-		goto err_clk_init_pmupstate;
+		goto err_perf_pmu_init_pmupstate;
 	}
 
 	err = vfe_var_sw_setup(g);
 	if (err != 0) {
-		goto err_clk_init_pmupstate;
+		goto err_perf_pmu_init_pmupstate;
 	}
 
 	err = vfe_equ_sw_setup(g);
 	if (err != 0) {
-		goto err_clk_init_pmupstate;
+		goto err_perf_pmu_init_pmupstate;
 	}
 
 	err = clk_domain_sw_setup(g);
 	if (err != 0) {
-		goto err_clk_init_pmupstate;
+		goto err_perf_pmu_init_pmupstate;
 	}
 
 	err = clk_vf_point_sw_setup(g);
 	if (err != 0) {
-		goto err_clk_init_pmupstate;
+		goto err_perf_pmu_init_pmupstate;
 	}
 
 	err = clk_prog_sw_setup(g);
 	if (err != 0) {
-		goto err_clk_init_pmupstate;
+		goto err_perf_pmu_init_pmupstate;
 	}
 
 	err = pstate_sw_setup(g);
 	if (err != 0) {
-		goto err_clk_init_pmupstate;
+		goto err_perf_pmu_init_pmupstate;
 	}
 
 	if(g->ops.clk.support_pmgr_domain) {
 		err = pmgr_domain_sw_setup(g);
 		if (err != 0) {
-			goto err_clk_init_pmupstate;
+			goto err_perf_pmu_init_pmupstate;
 		}
 	}
 
 	if (g->ops.clk.support_clk_freq_controller) {
 		err = clk_freq_controller_sw_setup(g);
 		if (err != 0) {
-			goto err_clk_init_pmupstate;
+			goto err_perf_pmu_init_pmupstate;
 		}
 	}
 
 	if(g->ops.clk.support_lpwr_pg) {
 		err = nvgpu_lpwr_pg_setup(g);
 		if (err != 0) {
-			goto err_clk_init_pmupstate;
+			goto err_perf_pmu_init_pmupstate;
 		}
 	}
 
 	return 0;
 
+err_perf_pmu_init_pmupstate:
+	perf_pmu_free_pmupstate(g);
 err_clk_init_pmupstate:
 	clk_free_pmupstate(g);
 	return err;
@@ -299,7 +307,7 @@ static struct pstate *pstate_construct(struct gk20a *g, void *args)
 
 static int pstate_insert(struct gk20a *g, struct pstate *pstate, int index)
 {
-	struct pstates *pstates = &(g->perf_pmu.pstatesobjs);
+	struct pstates *pstates = &(g->perf_pmu->pstatesobjs);
 	int err;
 
 	err = boardobjgrp_objinsert(&pstates->super.super,
@@ -425,14 +433,14 @@ static int pstate_sw_setup(struct gk20a *g)
 
 	nvgpu_log_fn(g, " ");
 
-	nvgpu_cond_init(&g->perf_pmu.pstatesobjs.pstate_notifier_wq);
+	nvgpu_cond_init(&g->perf_pmu->pstatesobjs.pstate_notifier_wq);
 
-	err = nvgpu_mutex_init(&g->perf_pmu.pstatesobjs.pstate_mutex);
+	err = nvgpu_mutex_init(&g->perf_pmu->pstatesobjs.pstate_mutex);
 	if (err != 0) {
 		return err;
 	}
 
-	err = boardobjgrpconstruct_e32(g, &g->perf_pmu.pstatesobjs.super);
+	err = boardobjgrpconstruct_e32(g, &g->perf_pmu->pstatesobjs.super);
 	if (err != 0) {
 		nvgpu_err(g,
 			  "error creating boardobjgrp for pstates, err=%d",
@@ -460,14 +468,14 @@ static int pstate_sw_setup(struct gk20a *g)
 	err = parse_pstate_table_5x(g, hdr);
 done:
 	if (err != 0) {
-		nvgpu_mutex_destroy(&g->perf_pmu.pstatesobjs.pstate_mutex);
+		nvgpu_mutex_destroy(&g->perf_pmu->pstatesobjs.pstate_mutex);
 	}
 	return err;
 }
 
 struct pstate *pstate_find(struct gk20a *g, u32 num)
 {
-	struct pstates *pstates = &(g->perf_pmu.pstatesobjs);
+	struct pstates *pstates = &(g->perf_pmu->pstatesobjs);
 	struct pstate *pstate;
 	u8 i;
 
diff --git a/drivers/gpu/nvgpu/volt/volt_dev.c b/drivers/gpu/nvgpu/volt/volt_dev.c
index aaa4d609e..f2fa4d434 100644
--- a/drivers/gpu/nvgpu/volt/volt_dev.c
+++ b/drivers/gpu/nvgpu/volt/volt_dev.c
@@ -31,6 +31,7 @@
 #include <nvgpu/string.h>
 #include <nvgpu/pmuif/ctrlvolt.h>
 
+#include "pmu_perf/pmu_perf.h"
 #include "gp106/bios_gp106.h"
 
 #include "volt.h"
@@ -502,7 +503,7 @@ static int volt_device_state_init(struct gk20a *g,
 
 	/* Build VOLT_RAIL SW state from VOLT_DEVICE SW state. */
 	/* If VOLT_RAIL isn't supported, exit. */
-	if (VOLT_RAIL_VOLT_3X_SUPPORTED(&g->perf_pmu.volt)) {
+	if (VOLT_RAIL_VOLT_3X_SUPPORTED(&g->perf_pmu->volt)) {
 		rail_idx = volt_rail_volt_domain_convert_to_idx(g,
 				pvolt_dev->volt_domain);
 		if (rail_idx == CTRL_BOARDOBJ_IDX_INVALID) {
@@ -512,7 +513,7 @@ static int volt_device_state_init(struct gk20a *g,
 			goto done;
 		}
 
-		pRail = VOLT_GET_VOLT_RAIL(&g->perf_pmu.volt, rail_idx);
+		pRail = VOLT_GET_VOLT_RAIL(&g->perf_pmu->volt, rail_idx);
 		if (pRail == NULL) {
 			nvgpu_err(g,
 				"could not obtain ptr to rail object from rail index");
@@ -544,7 +545,7 @@ int volt_dev_pmu_setup(struct gk20a *g)
 
 	nvgpu_log_info(g, " ");
 
-	pboardobjgrp = &g->perf_pmu.volt.volt_dev_metadata.volt_devices.super;
+	pboardobjgrp = &g->perf_pmu->volt.volt_dev_metadata.volt_devices.super;
 
 	if (!pboardobjgrp->bconstructed) {
 		return -EINVAL;
@@ -566,7 +567,7 @@ int volt_dev_sw_setup(struct gk20a *g)
 	nvgpu_log_info(g, " ");
 
 	status = boardobjgrpconstruct_e32(g,
-			&g->perf_pmu.volt.volt_dev_metadata.volt_devices);
+			&g->perf_pmu->volt.volt_dev_metadata.volt_devices);
 	if (status != 0) {
 		nvgpu_err(g,
 			"error creating boardobjgrp for volt rail, status - 0x%x",
@@ -574,13 +575,13 @@ int volt_dev_sw_setup(struct gk20a *g)
 		goto done;
 	}
 
-	pboardobjgrp = &g->perf_pmu.volt.volt_dev_metadata.volt_devices.super;
+	pboardobjgrp = &g->perf_pmu->volt.volt_dev_metadata.volt_devices.super;
 
 	pboardobjgrp->pmudatainstget  = _volt_device_devgrp_pmudata_instget;
 	pboardobjgrp->pmustatusinstget  = _volt_device_devgrp_pmustatus_instget;
 
 	/* Obtain Voltage Rail Table from VBIOS */
-	status = volt_get_volt_devices_table(g, &g->perf_pmu.volt.
+	status = volt_get_volt_devices_table(g, &g->perf_pmu->volt.
 			volt_dev_metadata);
 	if (status != 0) {
 		goto done;
@@ -599,7 +600,7 @@ int volt_dev_sw_setup(struct gk20a *g)
 	}
 
 	status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
-			&g->perf_pmu.volt.volt_dev_metadata.volt_devices.super,
+			&g->perf_pmu->volt.volt_dev_metadata.volt_devices.super,
 			volt, VOLT, volt_device, VOLT_DEVICE);
 	if (status != 0) {
 		nvgpu_err(g,
@@ -609,7 +610,7 @@ int volt_dev_sw_setup(struct gk20a *g)
 	}
 
 	/* update calibration to fuse */
-	BOARDOBJGRP_FOR_EACH(&(g->perf_pmu.volt.volt_dev_metadata.volt_devices.
+	BOARDOBJGRP_FOR_EACH(&(g->perf_pmu->volt.volt_dev_metadata.volt_devices.
 			       super),
 			     struct voltage_device *, pvolt_device, i) {
 		status = volt_device_state_init(g, pvolt_device);
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c
index 20380f00e..0570614b5 100644
--- a/drivers/gpu/nvgpu/volt/volt_pmu.c
+++ b/drivers/gpu/nvgpu/volt/volt_pmu.c
@@ -28,6 +28,7 @@
 #include <nvgpu/pmuif/ctrlvolt.h>
 #include <nvgpu/pmuif/ctrlperf.h>
 
+#include "pmu_perf/pmu_perf.h"
 #include "gp106/bios_gp106.h"
 
 #include "volt.h"
@@ -160,7 +161,7 @@ int nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g,
 
 	rail_idx = volt_rail_volt_domain_convert_to_idx(g, volt_domain);
 	if ((rail_idx == CTRL_VOLT_RAIL_INDEX_INVALID) ||
-		(!VOLT_RAIL_INDEX_IS_VALID(&g->perf_pmu.volt, rail_idx))) {
+		(!VOLT_RAIL_INDEX_IS_VALID(&g->perf_pmu->volt, rail_idx))) {
 		nvgpu_err(g,
 			"failed: volt_domain = %d, voltage rail table = %d.",
 			volt_domain, rail_idx);
@@ -195,7 +196,7 @@ int nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g,
 
 	rail_idx = volt_rail_volt_domain_convert_to_idx(g, volt_domain);
 	if ((rail_idx == CTRL_VOLT_RAIL_INDEX_INVALID) ||
-		(!VOLT_RAIL_INDEX_IS_VALID(&g->perf_pmu.volt, rail_idx))) {
+		(!VOLT_RAIL_INDEX_IS_VALID(&g->perf_pmu->volt, rail_idx))) {
 		nvgpu_err(g,
 			"failed: volt_domain = %d, voltage rail table = %d.",
 			volt_domain, rail_idx);
@@ -221,7 +222,7 @@ static int volt_policy_set_voltage(struct gk20a *g, u8 client_id,
 		struct ctrl_perf_volt_rail_list *prail_list)
 {
 	struct nv_pmu_volt_rpc rpc_call = { 0 };
-	struct obj_volt *pvolt = &g->perf_pmu.volt;
+	struct obj_volt *pvolt = &g->perf_pmu->volt;
 	int status = 0;
 	u8 policy_idx = CTRL_VOLT_POLICY_INDEX_INVALID;
 	u8 i = 0;
diff --git a/drivers/gpu/nvgpu/volt/volt_policy.c b/drivers/gpu/nvgpu/volt/volt_policy.c
index 035614c65..d5a317b5b 100644
--- a/drivers/gpu/nvgpu/volt/volt_policy.c
+++ b/drivers/gpu/nvgpu/volt/volt_policy.c
@@ -27,6 +27,7 @@
 #include <nvgpu/string.h>
 #include <nvgpu/pmuif/ctrlvolt.h>
 
+#include "pmu_perf/pmu_perf.h"
 #include "gp106/bios_gp106.h"
 
 #include "volt.h"
@@ -479,7 +480,7 @@ int volt_policy_pmu_setup(struct gk20a *g)
 	nvgpu_log_info(g, " ");
 
 	pboardobjgrp =
-		&g->perf_pmu.volt.volt_policy_metadata.volt_policies.super;
+		&g->perf_pmu->volt.volt_policy_metadata.volt_policies.super;
 
 	if (!pboardobjgrp->bconstructed) {
 		return -EINVAL;
@@ -499,7 +500,7 @@ int volt_policy_sw_setup(struct gk20a *g)
 	nvgpu_log_info(g, " ");
 
 	status = boardobjgrpconstruct_e32(g,
-			&g->perf_pmu.volt.volt_policy_metadata.volt_policies);
+			&g->perf_pmu->volt.volt_policy_metadata.volt_policies);
 	if (status != 0) {
 		nvgpu_err(g,
 			"error creating boardobjgrp for volt rail, status - 0x%x",
@@ -508,14 +509,14 @@ int volt_policy_sw_setup(struct gk20a *g)
 	}
 
 	pboardobjgrp =
-		&g->perf_pmu.volt.volt_policy_metadata.volt_policies.super;
+		&g->perf_pmu->volt.volt_policy_metadata.volt_policies.super;
 
 	pboardobjgrp->pmudatainstget  = _volt_policy_devgrp_pmudata_instget;
 	pboardobjgrp->pmustatusinstget  = _volt_policy_devgrp_pmustatus_instget;
 	pboardobjgrp->pmudatainit = _volt_policy_grp_pmudatainit_super;
 
 	/* Obtain Voltage Rail Table from VBIOS */
-	status = volt_get_volt_policy_table(g, &g->perf_pmu.volt.
+	status = volt_get_volt_policy_table(g, &g->perf_pmu->volt.
 			volt_policy_metadata);
 	if (status != 0) {
 		goto done;
@@ -534,7 +535,7 @@ int volt_policy_sw_setup(struct gk20a *g)
 	}
 
 	status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
-		&g->perf_pmu.volt.volt_policy_metadata.volt_policies.super,
+		&g->perf_pmu->volt.volt_policy_metadata.volt_policies.super,
 			volt, VOLT, volt_policy, VOLT_POLICY);
 	if (status != 0) {
 		nvgpu_err(g,
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.c b/drivers/gpu/nvgpu/volt/volt_rail.c
index fa4ac6b20..3a8229444 100644
--- a/drivers/gpu/nvgpu/volt/volt_rail.c
+++ b/drivers/gpu/nvgpu/volt/volt_rail.c
@@ -27,13 +27,14 @@
 #include <nvgpu/string.h>
 #include <nvgpu/pmuif/ctrlvolt.h>
 
+#include "pmu_perf/pmu_perf.h"
 #include "gp106/bios_gp106.h"
 
 #include "volt.h"
 
 u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain)
 {
-	switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) {
+	switch (g->perf_pmu->volt.volt_rail_metadata.volt_domain_hal) {
 	case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL:
 		switch (volt_domain) {
 		case CTRL_VOLT_DOMAIN_LOGIC:
@@ -108,7 +109,7 @@ static int volt_rail_state_init(struct gk20a *g,
 
 	for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) {
 		pvolt_rail->volt_delta_uv[i] = (int)NV_PMU_VOLT_VALUE_0V_IN_UV;
-		g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i] =
+		g->perf_pmu->volt.volt_rail_metadata.ext_rel_delta_uv[i] =
 			NV_PMU_VOLT_VALUE_0V_IN_UV;
 	}
 
@@ -164,7 +165,7 @@ static int volt_rail_init_pmudata_super(struct gk20a *g,
 
 	for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) {
 		rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] +
-			(int)g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i];
+			(int)g->perf_pmu->volt.volt_rail_metadata.ext_rel_delta_uv[i];
 	}
 
 	status = boardobjgrpmask_export(&prail->volt_dev_mask.super,
@@ -225,7 +226,7 @@ static struct voltage_rail *construct_volt_rail(struct gk20a *g, void *pargs)
 u8 volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g,
 	u8 vbios_volt_domain)
 {
-	switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) {
+	switch (g->perf_pmu->volt.volt_rail_metadata.volt_domain_hal) {
 	case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL:
 		if (vbios_volt_domain == 0U) {
 			return CTRL_VOLT_DOMAIN_LOGIC;
@@ -251,7 +252,7 @@ int volt_rail_pmu_setup(struct gk20a *g)
 
 	nvgpu_log_info(g, " ");
 
-	pboardobjgrp = &g->perf_pmu.volt.volt_rail_metadata.volt_rails.super;
+	pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
 
 	if (!pboardobjgrp->bconstructed) {
 		return -EINVAL;
@@ -423,7 +424,7 @@ int volt_rail_sw_setup(struct gk20a *g)
 	nvgpu_log_info(g, " ");
 
 	status = boardobjgrpconstruct_e32(g,
-			&g->perf_pmu.volt.volt_rail_metadata.volt_rails);
+			&g->perf_pmu->volt.volt_rail_metadata.volt_rails);
 	if (status != 0) {
 		nvgpu_err(g,
 			"error creating boardobjgrp for volt rail, status - 0x%x",
@@ -431,16 +432,16 @@ int volt_rail_sw_setup(struct gk20a *g)
 		goto done;
 	}
 
-	pboardobjgrp = &g->perf_pmu.volt.volt_rail_metadata.volt_rails.super;
+	pboardobjgrp = &g->perf_pmu->volt.volt_rail_metadata.volt_rails.super;
 
 	pboardobjgrp->pmudatainstget  = _volt_rail_devgrp_pmudata_instget;
 	pboardobjgrp->pmustatusinstget  = _volt_rail_devgrp_pmustatus_instget;
 
-	g->perf_pmu.volt.volt_rail_metadata.pct_delta =
+	g->perf_pmu->volt.volt_rail_metadata.pct_delta =
 			NV_PMU_VOLT_VALUE_0V_IN_UV;
 
 	/* Obtain Voltage Rail Table from VBIOS */
-	status = volt_get_volt_rail_table(g, &g->perf_pmu.volt.
+	status = volt_get_volt_rail_table(g, &g->perf_pmu->volt.
 			volt_rail_metadata);
 	if (status != 0) {
 		goto done;
@@ -459,7 +460,7 @@ int volt_rail_sw_setup(struct gk20a *g)
 	}
 
 	status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
-		&g->perf_pmu.volt.volt_rail_metadata.volt_rails.super,
+		&g->perf_pmu->volt.volt_rail_metadata.volt_rails.super,
 			volt, VOLT, volt_rail, VOLT_RAIL);
 	if (status != 0) {
 		nvgpu_err(g,
@@ -469,7 +470,7 @@ int volt_rail_sw_setup(struct gk20a *g)
 	}
 
 	/* update calibration to fuse */
-	BOARDOBJGRP_FOR_EACH(&(g->perf_pmu.volt.volt_rail_metadata.
+	BOARDOBJGRP_FOR_EACH(&(g->perf_pmu->volt.volt_rail_metadata.
 			       volt_rails.super),
 			     struct voltage_rail *, pvolt_rail, i) {
 		status = volt_rail_state_init(g, pvolt_rail);