diff --git a/drivers/gpu/nvgpu/common/device.c b/drivers/gpu/nvgpu/common/device.c
index 0dcc777ed..40f8c7725 100644
--- a/drivers/gpu/nvgpu/common/device.c
+++ b/drivers/gpu/nvgpu/common/device.c
@@ -151,7 +151,7 @@ void nvgpu_device_cleanup(struct gk20a *g)
  *
  * Return a pointer to the device or NULL of the inst ID is out of range.
  */
-static struct nvgpu_device *dev_instance_from_devlist(
+static const struct nvgpu_device *dev_instance_from_devlist(
 	struct nvgpu_list_node *devlist, u32 inst_id)
 {
 	u32 i = 0U;
@@ -167,32 +167,24 @@ static struct nvgpu_device *dev_instance_from_devlist(
 	return NULL;
 }
 
-int nvgpu_device_get(struct gk20a *g,
-		     struct nvgpu_device *dev,
+const struct nvgpu_device *nvgpu_device_get(struct gk20a *g,
 		     u32 type, u32 inst_id)
 {
-	struct nvgpu_device *target;
+	const struct nvgpu_device *dev;
 	struct nvgpu_list_node *device_list;
 
 	if (type >= NVGPU_MAX_DEVTYPE) {
-		return -EINVAL;
+		return NULL;
 	}
 
 	device_list = &g->devs->devlist_heads[type];
-	target = dev_instance_from_devlist(device_list, inst_id);
+	dev = dev_instance_from_devlist(device_list, inst_id);
 
-	if (target == NULL) {
-		return -ENODEV;
+	if (dev == NULL) {
+		return NULL;
 	}
 
-	nvgpu_memcpy((u8 *)dev, (const u8 *)target, sizeof(*dev));
-
-	/*
-	 * Don't let the calling code get access to the underlying device table!
-	 */
-	nvgpu_init_list_node(&dev->dev_list_node);
-
-	return 0;
+	return dev;
 }
 
 u32 nvgpu_device_count(struct gk20a *g, u32 type)
@@ -213,7 +205,7 @@ u32 nvgpu_device_count(struct gk20a *g, u32 type)
  * Once a per-chip translation table exists we can translate and then do a
  * comparison.
  */
-bool nvgpu_device_is_ce(struct gk20a *g, struct nvgpu_device *dev)
+bool nvgpu_device_is_ce(struct gk20a *g, const struct nvgpu_device *dev)
 {
 	if (dev->type == NVGPU_DEVTYPE_COPY0 ||
 	    dev->type == NVGPU_DEVTYPE_COPY1 ||
@@ -225,7 +217,7 @@ bool nvgpu_device_is_ce(struct gk20a *g, struct nvgpu_device *dev)
 	return false;
 }
 
-bool nvgpu_device_is_graphics(struct gk20a *g, struct nvgpu_device *dev)
+bool nvgpu_device_is_graphics(struct gk20a *g, const struct nvgpu_device *dev)
 {
 	return dev->type == NVGPU_DEVTYPE_GRAPHICS;
 }
diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c
index 3b6629792..f3b9b183a 100644
--- a/drivers/gpu/nvgpu/common/fifo/engines.c
+++ b/drivers/gpu/nvgpu/common/fifo/engines.c
@@ -47,7 +47,7 @@
 #define FECS_METHOD_WFI_RESTORE	0x80000U
 
 enum nvgpu_fifo_engine nvgpu_engine_enum_from_dev(struct gk20a *g,
-						  struct nvgpu_device *dev)
+			const struct nvgpu_device *dev)
 {
 	enum nvgpu_fifo_engine ret = NVGPU_ENGINE_INVAL;
 
@@ -802,53 +802,51 @@ int nvgpu_engine_init_info(struct nvgpu_fifo *f)
 	enum nvgpu_fifo_engine engine_enum;
 	u32 pbdma_id = U32_MAX;
 	bool found_pbdma_for_runlist = false;
-	struct nvgpu_device dev_info;
 	struct nvgpu_engine_info *info;
+	const struct nvgpu_device *dev;
 
 	f->num_engines = 0;
 
-	ret = nvgpu_device_get(g, &dev_info, NVGPU_DEVTYPE_GRAPHICS, 0);
-	if (ret != 0) {
-		nvgpu_err(g,
-			"Failed to parse dev_info table for engine %d",
-			NVGPU_DEVTYPE_GRAPHICS);
+	dev = nvgpu_device_get(g, NVGPU_DEVTYPE_GRAPHICS, 0);
+	if (dev == NULL) {
+		nvgpu_err(g, "Failed to get graphics engine %d", 0);
 		return -EINVAL;
 	}
 
 	found_pbdma_for_runlist = g->ops.pbdma.find_for_runlist(g,
-						dev_info.runlist_id,
+						dev->runlist_id,
 						&pbdma_id);
 	if (!found_pbdma_for_runlist) {
 		nvgpu_err(g, "busted pbdma map");
 		return -EINVAL;
 	}
 
-	engine_enum = nvgpu_engine_enum_from_dev(g, &dev_info);
+	engine_enum = nvgpu_engine_enum_from_dev(g, dev);
 
-	info = &g->fifo.engine_info[dev_info.engine_id];
+	info = &g->fifo.engine_info[dev->engine_id];
 
-	info->intr_mask |= BIT32(dev_info.intr_id);
-	info->reset_mask |= BIT32(dev_info.reset_id);
-	info->runlist_id = dev_info.runlist_id;
+	info->intr_mask |= BIT32(dev->intr_id);
+	info->reset_mask |= BIT32(dev->reset_id);
+	info->runlist_id = dev->runlist_id;
 	info->pbdma_id = pbdma_id;
-	info->inst_id  = dev_info.inst_id;
-	info->pri_base = dev_info.pri_base;
+	info->inst_id  = dev->inst_id;
+	info->pri_base = dev->pri_base;
 	info->engine_enum = engine_enum;
-	info->fault_id = dev_info.fault_id;
+	info->fault_id = dev->fault_id;
 
 	/* engine_id starts from 0 to NV_HOST_NUM_ENGINES */
-	f->active_engines_list[f->num_engines] = dev_info.engine_id;
+	f->active_engines_list[f->num_engines] = dev->engine_id;
 	++f->num_engines;
 	nvgpu_log_info(g,
 		"gr info: engine_id %d runlist_id %d intr_id %d "
 		"reset_id %d engine_type %d engine_enum %d inst_id %d",
-		dev_info.engine_id,
-		dev_info.runlist_id,
-		dev_info.intr_id,
-		dev_info.reset_id,
-		dev_info.type,
+		dev->engine_id,
+		dev->runlist_id,
+		dev->intr_id,
+		dev->reset_id,
+		dev->type,
 		engine_enum,
-		dev_info.inst_id);
+		dev->inst_id);
 
 	ret = g->ops.engine.init_ce_info(f);
 
diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink.c b/drivers/gpu/nvgpu/common/nvlink/nvlink.c
index d1d00bcdb..1172bc986 100644
--- a/drivers/gpu/nvgpu/common/nvlink/nvlink.c
+++ b/drivers/gpu/nvgpu/common/nvlink/nvlink.c
@@ -155,7 +155,6 @@ fail:
  */
 static int nvgpu_nvlink_discover_ioctrl(struct gk20a *g)
 {
-	int ret = 0;
 	u32 i;
 	struct nvgpu_nvlink_ioctrl_list *ioctrl_table;
 	u32 ioctrl_num_entries = 0U;
@@ -176,21 +175,20 @@ static int nvgpu_nvlink_discover_ioctrl(struct gk20a *g)
 	}
 
 	for (i = 0U; i < ioctrl_num_entries; i++) {
-		struct nvgpu_device dev_info;
+		const struct nvgpu_device *dev;
 
-		ret = nvgpu_device_get(g, &dev_info, NVGPU_DEVTYPE_IOCTRL, i);
-		if (ret != 0) {
-			nvgpu_err(g, "Failed to parse dev_info table"
-					"for engine %d",
-					NVGPU_DEVTYPE_IOCTRL);
+		dev = nvgpu_device_get(g, NVGPU_DEVTYPE_IOCTRL, i);
+		if (dev == NULL) {
+			nvgpu_err(g, "Failed to parse dev_info table IOCTRL dev (%d)",
+				  NVGPU_DEVTYPE_IOCTRL);
 			nvgpu_kfree(g, ioctrl_table);
 			return -EINVAL;
 		}
 
 		ioctrl_table[i].valid = true;
-		ioctrl_table[i].intr_enum = dev_info.intr_id;
-		ioctrl_table[i].reset_enum = dev_info.reset_id;
-		ioctrl_table[i].pri_base_addr = dev_info.pri_base;
+		ioctrl_table[i].intr_enum = dev->intr_id;
+		ioctrl_table[i].reset_enum = dev->reset_id;
+		ioctrl_table[i].pri_base_addr = dev->pri_base;
 		nvgpu_log(g, gpu_dbg_nvlink,
 			"Dev %d: Pri_Base = 0x%0x Intr = %d Reset = %d",
 			i, ioctrl_table[i].pri_base_addr,
diff --git a/drivers/gpu/nvgpu/hal/fifo/engines_gm20b.c b/drivers/gpu/nvgpu/hal/fifo/engines_gm20b.c
index 7a042d735..743426a90 100644
--- a/drivers/gpu/nvgpu/hal/fifo/engines_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/fifo/engines_gm20b.c
@@ -38,7 +38,6 @@ bool gm20b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid)
 int gm20b_engine_init_ce_info(struct nvgpu_fifo *f)
 {
 	struct gk20a *g = f->g;
-	int ret = 0;
 	u32 i;
 	enum nvgpu_fifo_engine engine_enum;
 	u32 pbdma_id = U32_MAX;
@@ -49,11 +48,15 @@ int gm20b_engine_init_ce_info(struct nvgpu_fifo *f)
 	nvgpu_log_info(g, "gr_runlist_id: %d", gr_runlist_id);
 
 	for (i = NVGPU_DEVTYPE_COPY0;  i <= NVGPU_DEVTYPE_COPY2; i++) {
-		struct nvgpu_device dev_info;
+		struct nvgpu_device *dev;
 		struct nvgpu_engine_info *info;
 
-		ret = nvgpu_device_get(g, &dev_info, i, 0);
-		if (ret != 0) {
+		/*
+		 * Cast to a non-const version since we have to hack up a few fields for
+		 * SW to work.
+		 */
+		dev = (struct nvgpu_device *)nvgpu_device_get(g, i, 0);
+		if (dev == NULL) {
 			/*
 			 * Not an error condition; gm20b has only 1 CE.
 			 */
@@ -61,56 +64,54 @@ int gm20b_engine_init_ce_info(struct nvgpu_fifo *f)
 		}
 
 		found_pbdma_for_runlist = g->ops.pbdma.find_for_runlist(g,
-							dev_info.runlist_id,
+							dev->runlist_id,
 							&pbdma_id);
 		if (!found_pbdma_for_runlist) {
 			nvgpu_err(g, "busted pbdma map");
 			return -EINVAL;
 		}
 
-		info = &g->fifo.engine_info[dev_info.engine_id];
+		info = &g->fifo.engine_info[dev->engine_id];
 
-		engine_enum = nvgpu_engine_enum_from_dev(g, &dev_info);
+		engine_enum = nvgpu_engine_enum_from_dev(g, dev);
 
 		/* GR and GR_COPY shares same runlist_id */
 		if ((engine_enum == NVGPU_ENGINE_ASYNC_CE) &&
-		    (gr_runlist_id == dev_info.runlist_id)) {
+		    (gr_runlist_id == dev->runlist_id)) {
 			engine_enum = NVGPU_ENGINE_GRCE;
 		}
 		info->engine_enum = engine_enum;
 
 		if (g->ops.top.get_ce_inst_id != NULL) {
-			dev_info.inst_id = g->ops.top.get_ce_inst_id(g,
-							     dev_info.type);
+			dev->inst_id = g->ops.top.get_ce_inst_id(g, dev->type);
 		}
 
-		if ((dev_info.fault_id == 0U) &&
+		if ((dev->fault_id == 0U) &&
 		    (engine_enum == NVGPU_ENGINE_GRCE)) {
-			dev_info.fault_id = 0x1b;
+			dev->fault_id = 0x1b;
 		}
 
-		info->fault_id = dev_info.fault_id;
-		info->intr_mask |= BIT32(dev_info.intr_id);
-		info->reset_mask |= BIT32(dev_info.reset_id);
-		info->runlist_id = dev_info.runlist_id;
+		info->fault_id = dev->fault_id;
+		info->intr_mask |= BIT32(dev->intr_id);
+		info->reset_mask |= BIT32(dev->reset_id);
+		info->runlist_id = dev->runlist_id;
 		info->pbdma_id = pbdma_id;
-		info->inst_id  = dev_info.inst_id;
-		info->pri_base = dev_info.pri_base;
+		info->inst_id  = dev->inst_id;
+		info->pri_base = dev->pri_base;
 
 		/* engine_id starts from 0 to NV_HOST_NUM_ENGINES */
-		f->active_engines_list[f->num_engines] =
-			dev_info.engine_id;
+		f->active_engines_list[f->num_engines] = dev->engine_id;
 		++f->num_engines;
 		nvgpu_log_info(g, "gr info: engine_id %d runlist_id %d "
 			       "intr_id %d reset_id %d type %d "
 			       "engine_enum %d inst_id %d",
-			       dev_info.engine_id,
-			       dev_info.runlist_id,
-			       dev_info.intr_id,
-			       dev_info.reset_id,
-			       dev_info.type,
+			       dev->engine_id,
+			       dev->runlist_id,
+			       dev->intr_id,
+			       dev->reset_id,
+			       dev->type,
 			       engine_enum,
-			       dev_info.inst_id);
+			       dev->inst_id);
 	}
 
 	return 0;
diff --git a/drivers/gpu/nvgpu/hal/fifo/engines_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/engines_gp10b_fusa.c
index f4ed37721..092246326 100644
--- a/drivers/gpu/nvgpu/hal/fifo/engines_gp10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/fifo/engines_gp10b_fusa.c
@@ -34,7 +34,6 @@
 int gp10b_engine_init_ce_info(struct nvgpu_fifo *f)
 {
 	struct gk20a *g = f->g;
-	int ret = 0;
 	u32 i;
 	enum nvgpu_fifo_engine engine_enum;
 	u32 gr_runlist_id;
@@ -49,71 +48,56 @@ int gp10b_engine_init_ce_info(struct nvgpu_fifo *f)
 	nvgpu_log_info(g, "lce_num_entries: %d", lce_num_entries);
 
 	for (i = 0; i < lce_num_entries; i++) {
-		struct nvgpu_device dev_info;
+		const struct nvgpu_device *dev;
 		struct nvgpu_engine_info *info;
 
-		ret = nvgpu_device_get(g, &dev_info, NVGPU_DEVTYPE_LCE, i);
-		if (ret != 0) {
-			nvgpu_err(g,
-				"Failed to parse dev_info for engine%d",
-				NVGPU_DEVTYPE_LCE);
+		dev = nvgpu_device_get(g, NVGPU_DEVTYPE_LCE, i);
+		if (dev == NULL) {
+			nvgpu_err(g, "Failed to get LCE device %u", i);
 			return -EINVAL;
 		}
 
 		found_pbdma_for_runlist =
 				g->ops.pbdma.find_for_runlist(g,
-						dev_info.runlist_id,
+						dev->runlist_id,
 						&pbdma_id);
 		if (!found_pbdma_for_runlist) {
 			nvgpu_err(g, "busted pbdma map");
 			return -EINVAL;
 		}
 
-		info = &g->fifo.engine_info[dev_info.engine_id];
+		info = &g->fifo.engine_info[dev->engine_id];
 
-		engine_enum = nvgpu_engine_enum_from_dev(g, &dev_info);
+		engine_enum = nvgpu_engine_enum_from_dev(g, dev);
 		/* GR and GR_COPY shares same runlist_id */
 		if ((engine_enum == NVGPU_ENGINE_ASYNC_CE) &&
-				(gr_runlist_id ==
-					dev_info.runlist_id)) {
+		    (gr_runlist_id == dev->runlist_id)) {
 			engine_enum = NVGPU_ENGINE_GRCE;
 		}
 		info->engine_enum = engine_enum;
 
-		if (g->ops.top.get_ce_inst_id != NULL) {
-			dev_info.inst_id = g->ops.top.get_ce_inst_id(g,
-						dev_info.type);
-		}
-
-		if ((dev_info.fault_id == 0U) &&
-				(engine_enum == NVGPU_ENGINE_GRCE)) {
-			dev_info.fault_id = 0x1b;
-		}
-		info->fault_id = dev_info.fault_id;
-
-
-		info->intr_mask |= BIT32(dev_info.intr_id);
-		info->reset_mask |= BIT32(dev_info.reset_id);
-		info->runlist_id = dev_info.runlist_id;
+		info->fault_id = dev->fault_id;
+		info->intr_mask |= BIT32(dev->intr_id);
+		info->reset_mask |= BIT32(dev->reset_id);
+		info->runlist_id = dev->runlist_id;
 		info->pbdma_id = pbdma_id;
-		info->inst_id  = dev_info.inst_id;
-		info->pri_base = dev_info.pri_base;
-		info->engine_id = dev_info.engine_id;
+		info->inst_id  = dev->inst_id;
+		info->pri_base = dev->pri_base;
+		info->engine_id = dev->engine_id;
 
 		/* engine_id starts from 0 to NV_HOST_NUM_ENGINES */
-		f->active_engines_list[f->num_engines] =
-						dev_info.engine_id;
+		f->active_engines_list[f->num_engines] = dev->engine_id;
 		f->num_engines = nvgpu_safe_add_u32(f->num_engines, 1U);
 		nvgpu_log_info(g, "gr info: engine_id %d runlist_id %d "
 			"intr_id %d reset_id %d engine_type %d "
 			"engine_enum %d inst_id %d",
-			dev_info.engine_id,
-			dev_info.runlist_id,
-			dev_info.intr_id,
-			dev_info.reset_id,
-			dev_info.type,
+			dev->engine_id,
+			dev->runlist_id,
+			dev->intr_id,
+			dev->reset_id,
+			dev->type,
 			engine_enum,
-			dev_info.inst_id);
+			dev->inst_id);
 	}
 	return 0;
 }
diff --git a/drivers/gpu/nvgpu/include/nvgpu/device.h b/drivers/gpu/nvgpu/include/nvgpu/device.h
index 05a0c3ebe..c12580add 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/device.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/device.h
@@ -179,9 +179,8 @@ void nvgpu_device_cleanup(struct gk20a *g);
  * device pointer. The device copied is chosen based on the \a type and
  * \a inst_id fields provided.
  */
-int nvgpu_device_get(struct gk20a *g,
-		     struct nvgpu_device *dev_info,
-		     u32 type, u32 inst_id);
+const struct nvgpu_device *nvgpu_device_get(struct gk20a *g,
+					    u32 type, u32 inst_id);
 
 /**
  * @brief Return number of devices of type \a type.
@@ -200,7 +199,7 @@ u32 nvgpu_device_count(struct gk20a *g, u32 type);
  * Returns true if \a dev matches a copy engine device type. For pre-Pascal
  * chips this is COPY[0, 1, 2], for Pascal and onward this is LCE.
  */
-bool nvgpu_device_is_ce(struct gk20a *g, struct nvgpu_device *dev);
+bool nvgpu_device_is_ce(struct gk20a *g, const struct nvgpu_device *dev);
 
 /**
  * @brief Return true if dev is a graphics device.
@@ -210,6 +209,6 @@ bool nvgpu_device_is_ce(struct gk20a *g, struct nvgpu_device *dev);
  *
  * Returns true if \a dev matches the graphics device type.
  */
-bool nvgpu_device_is_graphics(struct gk20a *g, struct nvgpu_device *dev);
+bool nvgpu_device_is_graphics(struct gk20a *g, const struct nvgpu_device *dev);
 
 #endif /* NVGPU_DEVICE_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/engines.h b/drivers/gpu/nvgpu/include/nvgpu/engines.h
index 6f3373b00..532d5ee82 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/engines.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/engines.h
@@ -127,7 +127,7 @@ struct nvgpu_engine_info {
  *         types for gr and/or ce engines.
  */
 enum nvgpu_fifo_engine nvgpu_engine_enum_from_dev(struct gk20a *g,
-						  struct nvgpu_device *dev);
+					const struct nvgpu_device *dev);
 /**
  * @brief Get pointer to #nvgpu_engine_info for the h/w engine id.
  *