From 167a2f91727a9dc7b3cb82fe39d3228a13ed716f Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Wed, 8 May 2019 10:29:43 -0400 Subject: [PATCH] gpu: nvgpu: init: fix MISRA 4.7 and 17.7 violations MISRA Rules 4.7 and 17.7 require the caller to check the return value of functions for errors. Update nvgpu_init.c to comply JIRA NVGPU-3318 Change-Id: I13c75f4d25f5dd79d8cce29ae22fbe1389e6bb96 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/2114659 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/init/nvgpu_init.c | 24 ++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c index 834d4bebb..dee970617 100644 --- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c +++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c @@ -307,7 +307,11 @@ int gk20a_finalize_poweron(struct gk20a *g) } if (g->ops.therm.elcg_init_idle_filters != NULL) { - g->ops.therm.elcg_init_idle_filters(g); + err = g->ops.therm.elcg_init_idle_filters(g); + if (err != 0) { + nvgpu_err(g, "failed to init elcg idle filters"); + goto done; + } } g->ops.mc.intr_enable(g); @@ -411,7 +415,11 @@ int gk20a_finalize_poweron(struct gk20a *g) if ((g->pmu.fw.ops.clk.clk_set_boot_clk != NULL) && nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) { - g->pmu.fw.ops.clk.clk_set_boot_clk(g); + err = g->pmu.fw.ops.clk.clk_set_boot_clk(g); + if (err != 0) { + nvgpu_err(g, "failed to set boot clk"); + goto done; + } } else { err = nvgpu_clk_arb_init_arbiter(g); if (err != 0) { @@ -437,7 +445,11 @@ int gk20a_finalize_poweron(struct gk20a *g) /* Restore the debug setting */ g->ops.fb.set_debug_mode(g, g->mmu_debug_ctrl); - nvgpu_ce_init_support(g); + err = nvgpu_ce_init_support(g); + if (err != 0) { + nvgpu_err(g, "failed to init ce"); + goto done; + } if (g->ops.xve.available_speeds != NULL) { u32 speed; @@ -463,8 +475,12 @@ int gk20a_finalize_poweron(struct gk20a *g) if (!nvgpu_mem_is_valid(&g->syncpt_mem)) { nr_pages = U32(DIV_ROUND_UP(g->syncpt_unit_size, PAGE_SIZE)); - nvgpu_mem_create_from_phys(g, &g->syncpt_mem, + err = nvgpu_mem_create_from_phys(g, &g->syncpt_mem, g->syncpt_unit_base, nr_pages); + if (err != 0) { + nvgpu_err(g, "Failed to create syncpt mem"); + goto done; + } } } #endif