gpu: nvgpu: move priv cmd definitions to channel

struct priv_cmd_queue and struct priv_cmd_entry are related to the list
of jobs in a channel, so move their definitions from the mm header to
the channel header.

Jira NVGPU-967

Change-Id: Ib0cf3fd52be463e720165a47e56b14724273473e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807371
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Holtta
2018-08-27 14:17:05 +03:00
committed by mobile promotions
parent 5a140928c2
commit 16ef96d4de
3 changed files with 18 additions and 17 deletions

View File

@@ -30,7 +30,7 @@
#include <nvgpu/cond.h> #include <nvgpu/cond.h>
#include <nvgpu/atomic.h> #include <nvgpu/atomic.h>
#include <nvgpu/nvgpu_mem.h> #include <nvgpu/nvgpu_mem.h>
#include <nvgpu/allocator.h>
struct gk20a; struct gk20a;
struct dbg_session_gk20a; struct dbg_session_gk20a;
@@ -109,6 +109,22 @@ struct notification {
u16 status; u16 status;
}; };
struct priv_cmd_queue {
struct nvgpu_mem mem;
u32 size; /* num of entries in words */
u32 put; /* put for priv cmd queue */
u32 get; /* get for priv cmd queue */
};
struct priv_cmd_entry {
bool valid;
struct nvgpu_mem *mem;
u32 off; /* offset in mem, in u32 entries */
u64 gva;
u32 get; /* start of entry in queue */
u32 size; /* in words */
};
struct channel_gk20a_job { struct channel_gk20a_job {
struct nvgpu_mapped_buf **mapped_buffers; struct nvgpu_mapped_buf **mapped_buffers;
int num_mapped_buffers; int num_mapped_buffers;

View File

@@ -45,6 +45,7 @@ struct nvgpu_clk_arb;
#ifdef CONFIG_GK20A_CTXSW_TRACE #ifdef CONFIG_GK20A_CTXSW_TRACE
struct nvgpu_ctxsw_trace_filter; struct nvgpu_ctxsw_trace_filter;
#endif #endif
struct priv_cmd_entry;
#include <nvgpu/lock.h> #include <nvgpu/lock.h>
#include <nvgpu/thread.h> #include <nvgpu/thread.h>

View File

@@ -85,22 +85,6 @@ gk20a_buffer_state_from_list(struct nvgpu_list_node *node)
((uintptr_t)node - offsetof(struct gk20a_buffer_state, list)); ((uintptr_t)node - offsetof(struct gk20a_buffer_state, list));
}; };
struct priv_cmd_queue {
struct nvgpu_mem mem;
u32 size; /* num of entries in words */
u32 put; /* put for priv cmd queue */
u32 get; /* get for priv cmd queue */
};
struct priv_cmd_entry {
bool valid;
struct nvgpu_mem *mem;
u32 off; /* offset in mem, in u32 entries */
u64 gva;
u32 get; /* start of entry in queue */
u32 size; /* in words */
};
struct gk20a; struct gk20a;
struct channel_gk20a; struct channel_gk20a;