From 173f23754d7d61709a767b3a512568eed19bcc84 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Wed, 8 May 2019 11:28:40 -0400 Subject: [PATCH] gpu:nvgpu: vbios: fix MISRA 21.2 violations MISRA Rule 21.2 prohibits naming identifiers beginning with double underscore. Rename __nvgpu_bios_readdbyte to nvgpu_bios_readbyte_impl to comply. JIRA NVGPU-3317 Change-Id: Ic5eaf0a629db8669c52cc6c8a2218499ceb0d8e4 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/2114878 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/vbios/bios.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/common/vbios/bios.c b/drivers/gpu/nvgpu/common/vbios/bios.c index 6df04f382..ee3bc9c5d 100644 --- a/drivers/gpu/nvgpu/common/vbios/bios.c +++ b/drivers/gpu/nvgpu/common/vbios/bios.c @@ -546,20 +546,20 @@ static void nvgpu_bios_parse_bit(struct gk20a *g, u32 offset) nvgpu_log_fn(g, "done"); } -static u32 __nvgpu_bios_readbyte(struct gk20a *g, u32 offset) +static u32 nvgpu_bios_readbyte_impl(struct gk20a *g, u32 offset) { return g->bios.data[offset]; } u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset) { - return (u8)__nvgpu_bios_readbyte(g, offset); + return (u8)nvgpu_bios_readbyte_impl(g, offset); } s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset) { u32 val; - val = __nvgpu_bios_readbyte(g, offset); + val = nvgpu_bios_readbyte_impl(g, offset); val = ((val & 0x80U) != 0U) ? (val | ~0xffU) : val; return (s8) val; @@ -569,8 +569,8 @@ u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset) { u16 val; - val = U16(__nvgpu_bios_readbyte(g, offset) | - (__nvgpu_bios_readbyte(g, offset+1U) << 8U)); + val = U16(nvgpu_bios_readbyte_impl(g, offset) | + (nvgpu_bios_readbyte_impl(g, offset+1U) << 8U)); return val; } @@ -579,10 +579,10 @@ u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset) { u32 val; - val = U32(__nvgpu_bios_readbyte(g, offset) | - (__nvgpu_bios_readbyte(g, offset+1U) << 8U) | - (__nvgpu_bios_readbyte(g, offset+2U) << 16U) | - (__nvgpu_bios_readbyte(g, offset+3U) << 24U)); + val = U32(nvgpu_bios_readbyte_impl(g, offset) | + (nvgpu_bios_readbyte_impl(g, offset+1U) << 8U) | + (nvgpu_bios_readbyte_impl(g, offset+2U) << 16U) | + (nvgpu_bios_readbyte_impl(g, offset+3U) << 24U)); return val; }