From 17607e6bc942c98d06e977487f47fe0d96065480 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Wed, 15 May 2019 18:57:54 +0530 Subject: [PATCH] gpu: nvgpu: remove sec2 from the safety build Since dGPU support is not required for initial safety release, disable features from dGPU. Remove sec2 to start. JIRA NVGPU-3062 Change-Id: I4448ab0fde603bc749dfdec5646308490971e18f Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/2119585 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/Makefile.shared.configs | 8 +++---- drivers/gpu/nvgpu/Makefile.sources | 23 +++++++++++-------- .../common/engine_queues/engine_mem_queue.c | 2 ++ drivers/gpu/nvgpu/common/gr/gr_falcon.c | 12 ++++++++-- drivers/gpu/nvgpu/common/init/nvgpu_init.c | 18 +++++++++++++-- drivers/gpu/nvgpu/common/pmu/pmu.c | 6 +++-- drivers/gpu/nvgpu/hal/init/hal_gv100.c | 6 +++++ drivers/gpu/nvgpu/hal/init/hal_tu104.c | 6 +++++ 9 files changed, 62 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 5d91b461f..559788896 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -28,6 +28,7 @@ endif ccflags-y += -DNVGPU_ENGINE ccflags-y += -DNVGPU_USERD ccflags-y += -DNVGPU_CHANNEL_WDT +ccflags-y += -DNVGPU_DGPU_SUPPORT obj-$(CONFIG_GK20A) := nvgpu.o diff --git a/drivers/gpu/nvgpu/Makefile.shared.configs b/drivers/gpu/nvgpu/Makefile.shared.configs index d06583fd2..0dc005160 100644 --- a/drivers/gpu/nvgpu/Makefile.shared.configs +++ b/drivers/gpu/nvgpu/Makefile.shared.configs @@ -41,10 +41,6 @@ NVGPU_COMMON_CFLAGS += -DNVGPU_LS_PMU NVGPU_COMMON_CFLAGS += -DNVGPU_ENGINE -# Enable dgpu support for safety build for now. To be removed. -NVGPU_DGPU_SUPPORT := 1 -NVGPU_COMMON_CFLAGS += -DNVGPU_DGPU_SUPPORT - ifeq ($(NV_BUILD_CONFIGURATION_IS_SAFETY),0) NVGPU_FECS_TRACE_SUPPORT := 1 NVGPU_COMMON_CFLAGS += -DCONFIG_GK20A_CTXSW_TRACE @@ -55,4 +51,8 @@ NVGPU_COMMON_CFLAGS += -DIGPU_VIRT_SUPPORT # Enable nvlink support for normal build. NVGPU_NVLINK_SUPPORT := 1 NVGPU_COMMON_CFLAGS += -DCONFIG_TEGRA_NVLINK + +# Enable dgpu support for normal build. +NVGPU_DGPU_SUPPORT := 1 +NVGPU_COMMON_CFLAGS += -DNVGPU_DGPU_SUPPORT endif diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 216443808..57f8b12c5 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -108,7 +108,6 @@ srcs += common/sim/sim.c \ common/falcon/falcon_sw_tu104.c \ common/engine_queues/engine_mem_queue.c \ common/engine_queues/engine_dmem_queue.c \ - common/engine_queues/engine_emem_queue.c \ common/engine_queues/engine_fb_queue.c \ common/gr/gr.c \ common/gr/gr_utils.c \ @@ -156,13 +155,6 @@ srcs += common/sim/sim.c \ common/acr/acr_sw_gv100.c \ common/acr/acr_sw_gv11b.c \ common/acr/acr_sw_tu104.c \ - common/sec2/sec2.c \ - common/sec2/sec2_allocator.c \ - common/sec2/sec2_lsfm.c \ - common/sec2/ipc/sec2_cmd.c \ - common/sec2/ipc/sec2_msg.c \ - common/sec2/ipc/sec2_queue.c \ - common/sec2/ipc/sec2_seq.c \ common/ptimer/ptimer.c \ common/worker.c \ common/sync/channel_sync.c \ @@ -416,8 +408,6 @@ srcs += common/sim/sim.c \ hal/nvdec/nvdec_gp106.c \ hal/nvdec/nvdec_tu104.c \ hal/gsp/gsp_gv100.c \ - hal/sec2/sec2_gp106.c \ - hal/sec2/sec2_tu104.c \ hal/sync/sema_cmdbuf_gk20a.c \ hal/sync/sema_cmdbuf_gv11b.c \ hal/sync/syncpt_cmdbuf_gk20a.c \ @@ -516,3 +506,16 @@ srcs += common/vbios/nvlink_bios.c \ hal/nvlink/link_mode_transitions_gv100.c \ hal/nvlink/link_mode_transitions_tu104.c endif + +ifeq ($(NVGPU_DGPU_SUPPORT), 1) +srcs += common/engine_queues/engine_emem_queue.c \ + common/sec2/sec2.c \ + common/sec2/sec2_allocator.c \ + common/sec2/sec2_lsfm.c \ + common/sec2/ipc/sec2_cmd.c \ + common/sec2/ipc/sec2_msg.c \ + common/sec2/ipc/sec2_queue.c \ + common/sec2/ipc/sec2_seq.c \ + hal/sec2/sec2_gp106.c \ + hal/sec2/sec2_tu104.c +endif diff --git a/drivers/gpu/nvgpu/common/engine_queues/engine_mem_queue.c b/drivers/gpu/nvgpu/common/engine_queues/engine_mem_queue.c index 5a09c1164..4c347dbf5 100644 --- a/drivers/gpu/nvgpu/common/engine_queues/engine_mem_queue.c +++ b/drivers/gpu/nvgpu/common/engine_queues/engine_mem_queue.c @@ -411,9 +411,11 @@ int nvgpu_engine_mem_queue_init(struct nvgpu_engine_mem_queue **queue_p, case QUEUE_TYPE_DMEM: engine_dmem_queue_init(queue); break; +#ifdef NVGPU_DGPU_SUPPORT case QUEUE_TYPE_EMEM: engine_emem_queue_init(queue); break; +#endif default: err = -EINVAL; break; diff --git a/drivers/gpu/nvgpu/common/gr/gr_falcon.c b/drivers/gpu/nvgpu/common/gr/gr_falcon.c index 55ed515cf..1ca858ffc 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_falcon.c +++ b/drivers/gpu/nvgpu/common/gr/gr_falcon.c @@ -32,7 +32,9 @@ #include #include #include +#ifdef NVGPU_DGPU_SUPPORT #include +#endif #include #include @@ -554,12 +556,15 @@ int nvgpu_gr_falcon_load_secure_ctxsw_ucode(struct gk20a *g, } else { /* bind WPR VA inst block */ nvgpu_gr_falcon_bind_instblk(g, falcon); +#ifdef NVGPU_DGPU_SUPPORT if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { err = nvgpu_sec2_bootstrap_ls_falcons(g, &g->sec2, FALCON_ID_FECS); err = nvgpu_sec2_bootstrap_ls_falcons(g, &g->sec2, FALCON_ID_GPCCS); - } else if (g->support_ls_pmu) { + } else +#endif + if (g->support_ls_pmu) { err = nvgpu_pmu_lsfm_bootstrap_ls_falcon(g, g->pmu, g->pmu->lsfm, BIT32(FALCON_ID_FECS) | @@ -594,12 +599,15 @@ int nvgpu_gr_falcon_load_secure_ctxsw_ucode(struct gk20a *g, falcon_id_mask |= BIT8(FALCON_ID_GPCCS); } +#ifdef NVGPU_DGPU_SUPPORT if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { err = nvgpu_sec2_bootstrap_ls_falcons(g, &g->sec2, FALCON_ID_FECS); err = nvgpu_sec2_bootstrap_ls_falcons(g, &g->sec2, FALCON_ID_GPCCS); - } else if (g->support_ls_pmu) { + } else +#endif + if (g->support_ls_pmu) { err = nvgpu_pmu_lsfm_bootstrap_ls_falcon(g, g->pmu, g->pmu->lsfm, falcon_id_mask); diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c index 86d2dde08..803c1b36d 100644 --- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c +++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c @@ -103,13 +103,14 @@ int gk20a_prepare_poweroff(struct gk20a *g) ret = nvgpu_pmu_destroy(g, g->pmu); } +#ifdef NVGPU_DGPU_SUPPORT if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { tmp_ret = nvgpu_sec2_destroy(g); if ((tmp_ret != 0) && (ret == 0)) { ret = tmp_ret; } } - +#endif tmp_ret = nvgpu_gr_suspend(g); if ((tmp_ret != 0) && (ret == 0)) { ret = tmp_ret; @@ -184,15 +185,23 @@ int gk20a_finalize_poweron(struct gk20a *g) nvgpu_err(g, "failed to sw init FALCON_ID_PMU"); goto exit; } + +#ifdef NVGPU_DGPU_SUPPORT err = nvgpu_falcon_sw_init(g, FALCON_ID_SEC2); if (err != 0) { nvgpu_err(g, "failed to sw init FALCON_ID_SEC2"); goto done_pmu; } +#endif + err = nvgpu_falcon_sw_init(g, FALCON_ID_NVDEC); if (err != 0) { nvgpu_err(g, "failed to sw init FALCON_ID_NVDEC"); +#ifdef NVGPU_DGPU_SUPPORT goto done_sec2; +#else + goto done_pmu; +#endif } err = nvgpu_falcon_sw_init(g, FALCON_ID_GSPLITE); if (err != 0) { @@ -211,6 +220,7 @@ int gk20a_finalize_poweron(struct gk20a *g) goto done; } +#ifdef NVGPU_DGPU_SUPPORT if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { err = nvgpu_init_sec2_setup_sw(g, &g->sec2); if (err != 0) { @@ -218,7 +228,7 @@ int gk20a_finalize_poweron(struct gk20a *g) goto done; } } - +#endif if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { /* Init chip specific ACR properties */ err = nvgpu_acr_init(g, &g->acr); @@ -359,6 +369,7 @@ int gk20a_finalize_poweron(struct gk20a *g) } } +#ifdef NVGPU_DGPU_SUPPORT if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { err = nvgpu_init_sec2_support(g); if (err != 0) { @@ -367,6 +378,7 @@ int gk20a_finalize_poweron(struct gk20a *g) goto done; } } +#endif err = nvgpu_pmu_init(g, g->pmu); if (err != 0) { @@ -497,8 +509,10 @@ done_gsp: nvgpu_falcon_sw_free(g, FALCON_ID_GSPLITE); done_nvdec: nvgpu_falcon_sw_free(g, FALCON_ID_NVDEC); +#ifdef NVGPU_DGPU_SUPPORT done_sec2: nvgpu_falcon_sw_free(g, FALCON_ID_SEC2); +#endif done_pmu: nvgpu_falcon_sw_free(g, FALCON_ID_PMU); exit: diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c index ad1e49468..1420ff45b 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu.c @@ -32,7 +32,9 @@ #include #include #include +#ifdef NVGPU_DGPU_SUPPORT #include +#endif #include #include #include @@ -221,7 +223,7 @@ int nvgpu_pmu_init(struct gk20a *g, struct nvgpu_pmu *pmu) } if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { - +#ifdef NVGPU_DGPU_SUPPORT if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { /* Reset PMU engine */ err = nvgpu_falcon_reset(g->pmu->flcn); @@ -233,7 +235,7 @@ int nvgpu_pmu_init(struct gk20a *g, struct nvgpu_pmu *pmu) goto exit; } } - +#endif /* * clear halt interrupt to avoid PMU-RTOS ucode * hitting breakpoint due to PMU halt diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv100.c b/drivers/gpu/nvgpu/hal/init/hal_gv100.c index fd1ec7aca..2cec1c654 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv100.c @@ -129,7 +129,9 @@ #include "hal/nvdec/nvdec_gp106.h" #include "hal/gsp/gsp_gv100.h" #include "hal/perf/perf_gv11b.h" +#ifdef NVGPU_DGPU_SUPPORT #include "hal/sec2/sec2_gp106.h" +#endif #include "hal/sync/syncpt_cmdbuf_gv11b.h" #include "hal/sync/sema_cmdbuf_gv11b.h" #include "hal/netlist/netlist_gv100.h" @@ -1310,11 +1312,13 @@ static const struct gpu_ops gv100_ops = { gp106_top_scratch1_devinit_completed, }, +#ifdef NVGPU_DGPU_SUPPORT .sec2 = { .falcon_base_addr = gp106_sec2_falcon_base_addr, .sec2_reset = gp106_sec2_reset, .flcn_setup_boot_config = gp106_sec2_flcn_setup_boot_config, }, +#endif .gsp = { .falcon_base_addr = gv100_gsp_falcon_base_addr, .falcon_setup_boot_config = gv100_gsp_flcn_setup_boot_config, @@ -1375,7 +1379,9 @@ int gv100_init_hal(struct gk20a *g) gops->fuse = gv100_ops.fuse; gops->nvlink = gv100_ops.nvlink; gops->top = gv100_ops.top; +#ifdef NVGPU_DGPU_SUPPORT gops->sec2 = gv100_ops.sec2; +#endif gops->gsp = gv100_ops.gsp; /* clocks */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 64bd11f06..5294abde4 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -145,7 +145,9 @@ #include "hal/nvdec/nvdec_tu104.h" #include "hal/gsp/gsp_gv100.h" #include "hal/perf/perf_gv11b.h" +#ifdef NVGPU_DGPU_SUPPORT #include "hal/sec2/sec2_tu104.h" +#endif #include "hal/sync/syncpt_cmdbuf_gv11b.h" #include "hal/sync/sema_cmdbuf_gv11b.h" #include "hal/netlist/netlist_tu104.h" @@ -1326,6 +1328,7 @@ static const struct gpu_ops tu104_ops = { } }, #endif +#ifdef NVGPU_DGPU_SUPPORT .sec2 = { .secured_sec2_start = tu104_start_sec2_secure, .enable_irq = tu104_sec2_enable_irq, @@ -1344,6 +1347,7 @@ static const struct gpu_ops tu104_ops = { .sec2_queue_tail = tu104_sec2_queue_tail, .flcn_setup_boot_config = tu104_sec2_flcn_setup_boot_config, }, +#endif .gsp = { .falcon_base_addr = gv100_gsp_falcon_base_addr, .falcon_setup_boot_config = gv100_gsp_flcn_setup_boot_config, @@ -1421,7 +1425,9 @@ int tu104_init_hal(struct gk20a *g) gops->priv_ring = tu104_ops.priv_ring; gops->fuse = tu104_ops.fuse; gops->nvlink = tu104_ops.nvlink; +#ifdef NVGPU_DGPU_SUPPORT gops->sec2 = tu104_ops.sec2; +#endif gops->gsp = tu104_ops.gsp; gops->top = tu104_ops.top;