From 1782bb435bfa030f3376047783f8d78b46c316bb Mon Sep 17 00:00:00 2001 From: Antony Clince Alex Date: Tue, 1 Jun 2021 06:30:22 +0000 Subject: [PATCH] gpu: nvgpu: ga10b, ga100: replace legacy pmasys control register Starting from Ampere+ chips, PMASYS control register layout has been re-organized to support multiple PMA streaming channels. In accordance with this update perf HALs to replace legacy register with new registers. The mapping between the legacy register and new register fields can be found here: http://nvbugs/2332044/16. Jira NVGPU-6906 Bug 200737354 Change-Id: I4ed5af7be04f7e2b97a8bf500de3a04cf1e4834c Signed-off-by: Antony Clince Alex Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2559392 Tested-by: mobile promotions Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: svc_kernel_abi Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/hal/perf/perf_ga10b.c | 14 +++++++------- .../include/nvgpu/hw/ga100/hw_perf_ga100.h | 18 +++++++++++++----- .../include/nvgpu/hw/ga10b/hw_perf_ga10b.h | 10 +++++----- 3 files changed, 25 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/perf/perf_ga10b.c b/drivers/gpu/nvgpu/hal/perf/perf_ga10b.c index 68e144cfa..1aa27de80 100644 --- a/drivers/gpu/nvgpu/hal/perf/perf_ga10b.c +++ b/drivers/gpu/nvgpu/hal/perf/perf_ga10b.c @@ -274,13 +274,13 @@ const u32 *ga10b_perf_get_hwpm_fbp_perfmon_regs(u32 *count) bool ga10b_perf_get_membuf_overflow_status(struct gk20a *g) { const u32 st = - perf_pmasys_channel_control_membuf_status_overflowed_f(); + perf_pmasys_channel_status_secure_membuf_status_overflowed_f(); - nvgpu_assert(perf_pmasys_channel_control__size_1_v() == + nvgpu_assert(perf_pmasys_channel_status_secure__size_1_v() == pmasys_channel_instance_max_size); return st == (nvgpu_readl(g, - perf_pmasys_channel_control_r(inst_zero)) & st); + perf_pmasys_channel_status_secure_r(inst_zero)) & st); } u32 ga10b_perf_get_membuf_pending_bytes(struct gk20a *g) @@ -311,7 +311,7 @@ void ga10b_perf_membuf_reset_streaming(struct gk20a *g) u32 num_unread_bytes; u32 i; - nvgpu_assert(perf_pmasys_channel_control__size_1_v() == + nvgpu_assert(perf_pmasys_channel_control_user__size_1_v() == pmasys_channel_instance_max_size); nvgpu_assert(perf_pmasys_channel_mem_bytes__size_1_v() == pmasys_channel_instance_max_size); @@ -322,9 +322,9 @@ void ga10b_perf_membuf_reset_streaming(struct gk20a *g) WARN_ON(0U == (engine_status & perf_pmasys_enginestatus_rbufempty_empty_f())); - for (i = 0U; i < perf_pmasys_channel_control__size_1_v(); i++) { - nvgpu_writel(g, perf_pmasys_channel_control_r(i), - perf_pmasys_channel_control_membuf_clear_status_doit_f()); + for (i = 0U; i < perf_pmasys_channel_control_user__size_1_v(); i++) { + nvgpu_writel(g, perf_pmasys_channel_control_user_r(i), + perf_pmasys_channel_control_user_membuf_clear_status_doit_f()); } for (i = 0U; i < perf_pmasys_channel_mem_bytes__size_1_v(); i++) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_perf_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_perf_ga100.h index cc49baaac..9ba5e5748 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_perf_ga100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_perf_ga100.h @@ -68,11 +68,19 @@ #define perf_pmmfbp_base_v() (0x00200000U) #define perf_pmmfbp_extent_v() (0x00203fffU) #define perf_pmasys_control_r() (0x0024a000U) -#define perf_pmasys_channel_control_r(i)\ - (nvgpu_safe_add_u32(0x0024a730U, nvgpu_safe_mult_u32((i), 4U))) -#define perf_pmasys_channel_control__size_1_v() (0x00000001U) -#define perf_pmasys_channel_control_membuf_status_overflowed_f() (0x10U) -#define perf_pmasys_channel_control_membuf_clear_status_doit_f() (0x20U) +#define perf_pmasys_channel_control_user_r(i)\ + (nvgpu_safe_add_u32(0x0024a620U, nvgpu_safe_mult_u32((i), 384U))) +#define perf_pmasys_channel_control_user__size_1_v() (0x00000001U) +#define perf_pmasys_channel_control_user_stream_m() (U32(0x1U) << 0U) +#define perf_pmasys_channel_control_user_stream_enable_f() (0x1U) +#define perf_pmasys_channel_control_user_stream_disable_f() (0x0U) +#define perf_pmasys_channel_control_user_update_bytes_m() (U32(0x1U) << 31U) +#define perf_pmasys_channel_control_user_update_bytes_doit_f() (0x80000000U) +#define perf_pmasys_channel_control_user_membuf_clear_status_doit_f() (0x2U) +#define perf_pmasys_channel_status_secure_r(i)\ + (nvgpu_safe_add_u32(0x0024a610U, nvgpu_safe_mult_u32((i), 384U))) +#define perf_pmasys_channel_status_secure__size_1_v() (0x00000001U) +#define perf_pmasys_channel_status_secure_membuf_status_overflowed_f() (0x1U) #define perf_pmasys_channel_mem_block_r(i)\ (nvgpu_safe_add_u32(0x0024a638U, nvgpu_safe_mult_u32((i), 4U))) #define perf_pmasys_channel_mem_block__size_1_v() (0x00000001U) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_perf_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_perf_ga10b.h index 0a27088e7..dbc32aad4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_perf_ga10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_perf_ga10b.h @@ -68,11 +68,6 @@ #define perf_pmmfbp_base_v() (0x00200000U) #define perf_pmmfbp_extent_v() (0x00203fffU) #define perf_pmasys_control_r() (0x0024a000U) -#define perf_pmasys_channel_control_r(i)\ - (nvgpu_safe_add_u32(0x0024a730U, nvgpu_safe_mult_u32((i), 4U))) -#define perf_pmasys_channel_control__size_1_v() (0x00000001U) -#define perf_pmasys_channel_control_membuf_status_overflowed_f() (0x10U) -#define perf_pmasys_channel_control_membuf_clear_status_doit_f() (0x20U) #define perf_pmasys_channel_control_user_r(i)\ (nvgpu_safe_add_u32(0x0024a620U, nvgpu_safe_mult_u32((i), 384U))) #define perf_pmasys_channel_control_user__size_1_v() (0x00000001U) @@ -81,6 +76,11 @@ #define perf_pmasys_channel_control_user_stream_disable_f() (0x0U) #define perf_pmasys_channel_control_user_update_bytes_m() (U32(0x1U) << 31U) #define perf_pmasys_channel_control_user_update_bytes_doit_f() (0x80000000U) +#define perf_pmasys_channel_control_user_membuf_clear_status_doit_f() (0x2U) +#define perf_pmasys_channel_status_secure_r(i)\ + (nvgpu_safe_add_u32(0x0024a610U, nvgpu_safe_mult_u32((i), 384U))) +#define perf_pmasys_channel_status_secure__size_1_v() (0x00000001U) +#define perf_pmasys_channel_status_secure_membuf_status_overflowed_f() (0x1U) #define perf_pmasys_channel_mem_block_r(i)\ (nvgpu_safe_add_u32(0x0024a638U, nvgpu_safe_mult_u32((i), 4U))) #define perf_pmasys_channel_mem_block__size_1_v() (0x00000001U)