gpu: nvgpu: Refactor Clock unit.

Current clk unit has multiple header files under pmuif folder.
This has combination of public struct which is accessed outside the
unit and private struct which is accessed within clk unit.
This patch segregates them based on their accessibility.
All private items are moved into ucode_clk_inf.h from pmuif which only
clk can access.
All public items are moved into include/clk.h which other units can
access
This will help in documentation of items for public items.

NVGPU-4491

Change-Id: Iccb0571e05ecb3cb13363390bed8c7214409b543
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292318
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

arch/nvgpu-common.yaml

@@ -643,8 +643,6 @@ pmu:
       # Subset of each interfaces should be distributed to individual units.
       # TODO!
       sources: [ include/nvgpu/pmu/pmuif/ctrlboardobj.h,
-                 include/nvgpu/pmu/pmuif/ctrlclk.h,
-                 include/nvgpu/pmu/pmuif/ctrlclkavfs.h,
                  include/nvgpu/pmu/pmuif/ctrlpmgr.h,
                  include/nvgpu/pmu/pmuif/acr.h,
                  include/nvgpu/pmu/pmuif/ap.h,
@@ -655,7 +653,6 @@ pmu:
                  include/nvgpu/pmu/pmuif/init.h,
                  include/nvgpu/pmu/pmuif/bios.h,
                  include/nvgpu/pmu/pmuif/boardobj.h,
-                 include/nvgpu/pmu/pmuif/clk.h,
                  include/nvgpu/pmu/pmuif/pmgr.h,
                  include/nvgpu/pmu/pmuif/seq.h,
                  include/nvgpu/pmu/pmuif/rpc.h,
@@ -768,6 +765,7 @@ pmu:
           safe: yes
           gpu: dgpu
           sources: [ common/pmu/clk/clk.c,
+                     common/pmu/clk/ucode_clk_inf.h,
                      include/nvgpu/clk.h,
                      include/nvgpu/pmu/clk/clk.h ]
 

drivers/gpu/nvgpu/common/clk_arb/clk_arb.c

@@ -35,9 +35,9 @@
 #include <nvgpu/worker.h>
 #include <nvgpu/gk20a.h>
 #ifdef CONFIG_NVGPU_LS_PMU
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/perf.h>
 #include <nvgpu/pmu/volt.h>
-#include <nvgpu/pmu/clk/clk.h>
 #endif
 #include <nvgpu/boardobjgrp_e255.h>
 

drivers/gpu/nvgpu/common/clk_arb/clk_arb_gp10b.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,6 +22,7 @@
 
 #include <nvgpu/gk20a.h>
 #include <nvgpu/clk_arb.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 #include "clk_arb_gp10b.h"
 

drivers/gpu/nvgpu/common/pmu/clk/clk.c

@@ -23,17 +23,17 @@
 #include <nvgpu/pmu.h>
 #include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
 #include <nvgpu/gk20a.h>
-#include <nvgpu/pmu/pmuif/ctrlclk.h>
 #include <nvgpu/bug.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/volt.h>
 #include <nvgpu/pmu/perf.h>
-#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/cmd.h>
 #include <nvgpu/timers.h>
 #include <nvgpu/pmu/pmu_pstate.h>
 #include <nvgpu/pmu/perf.h>
 #include <nvgpu/pmu/clk/clk_vf_point.h>
 
+#include "ucode_clk_inf.h"
 #include "clk_domain.h"
 #include "clk_prog.h"
 #include "clk_vin.h"

drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c

@@ -28,14 +28,14 @@
 #include <nvgpu/boardobjgrp_e255.h>
 #include <nvgpu/pmu/boardobjgrp_classes.h>
 #include <nvgpu/boardobjgrpmask.h>
-#include <nvgpu/pmu/pmuif/ctrlclk.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/clk/clk_vf_point.h>
 #include <nvgpu/pmu/perf.h>
 #include <nvgpu/string.h>
 #include <nvgpu/pmu/volt.h>
-#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/cmd.h>
 
+#include "ucode_clk_inf.h"
 #include "clk_domain.h"
 #include "clk_prog.h"
 

drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c

@@ -27,11 +27,11 @@
 #include <nvgpu/pmu/boardobjgrp_classes.h>
 #include <nvgpu/boardobjgrpmask.h>
 #include <nvgpu/string.h>
-#include <nvgpu/pmu/pmuif/ctrlclk.h>
 #include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/clk/clk_fll.h>
 #include <nvgpu/pmu/clk/clk_vin.h>
 
+#include "ucode_clk_inf.h"
 #include "clk_fll.h"
 
 #define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP	0x10U

drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c

@@ -28,10 +28,10 @@
 #include <nvgpu/boardobjgrp_e255.h>
 #include <nvgpu/pmu/boardobjgrp_classes.h>
 #include <nvgpu/string.h>
-#include <nvgpu/pmu/pmuif/ctrlclk.h>
 #include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/clk/clk_vf_point.h>
 
+#include "ucode_clk_inf.h"
 #include "clk_prog.h"
 
 static struct clk_prog *construct_clk_prog(struct gk20a *g, void *pargs);

drivers/gpu/nvgpu/common/pmu/clk/clk_prog.h

@@ -23,7 +23,6 @@
 #ifndef NVGPU_CLK_PROG_H
 #define NVGPU_CLK_PROG_H
 
-#include <nvgpu/pmu/pmuif/ctrlclk.h>
 #include <nvgpu/pmu/pmuif/ctrlboardobj.h>
 #include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
 #include <nvgpu/boardobjgrp_e32.h>

drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c

@@ -26,16 +26,15 @@
 #include <nvgpu/boardobjgrp_e255.h>
 #include <nvgpu/pmu/boardobjgrp_classes.h>
 #include <nvgpu/string.h>
-#include <nvgpu/pmu/pmuif/ctrlclk.h>
 #include <nvgpu/timers.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/clk_arb.h>
 #include <nvgpu/pmu/volt.h>
 #include <nvgpu/pmu/perf.h>
-#include <nvgpu/pmu/pmuif/clk.h>
-#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/clk/clk_vf_point.h>
 #include <nvgpu/pmu/cmd.h>
 
+#include "ucode_clk_inf.h"
 #include "clk_vf_point.h"
 
 int nvgpu_clk_domain_volt_to_freq(struct gk20a *g, u8 clkdomain_idx,

drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c

@@ -33,6 +33,7 @@
 #include <nvgpu/pmu/cmd.h>
 #include <nvgpu/pmu/volt.h>
 
+#include "ucode_clk_inf.h"
 #include "clk_vin.h"
 
 static int devinit_get_vin_device_table(struct gk20a *g,

drivers/gpu/nvgpu/common/pmu/clk/ucode_clk_inf.h

@@ -25,37 +25,215 @@
 
 #include <nvgpu/flcnif_cmn.h>
 #include <nvgpu/pmu/volt.h>
+#include <nvgpu/pmu/pmuif/ctrlboardobj.h>
+#include <nvgpu/pmu/pmuif/boardobj.h>
 
-#include "ctrlboardobj.h"
+/*!
-#include "ctrlclk.h"
+ * Various types of VIN calibration that the GPU can support
-#include "boardobj.h"
-
-/*
- *  Try to get gpc2clk, mclk, sys2clk, xbar2clk work for Pascal
- *
- *  mclk is same for both
- *  gpc2clk is 17 for Pascal and 13 for Volta, making it 17
- *    as volta uses gpcclk
- *  sys2clk is 20 in Pascal and 15 in Volta.
- *    Changing for Pascal would break nvdclk of Volta
- *  xbar2clk is 19 in Pascal and 14 in Volta
- *    Changing for Pascal would break pwrclk of Volta
  */
-#define CLKWHICH_GPCCLK		1U
+#define CTRL_CLK_VIN_CAL_TYPE_V20           (0x00000001U)
-#define CLKWHICH_XBARCLK	2U
+
-#define CLKWHICH_SYSCLK		3U
+#define CTRL_CLK_VIN_VFE_IDX_INVALID		(0xFFU)
-#define CLKWHICH_HUBCLK		4U
+
-#define CLKWHICH_MCLK		5U
+/*!
-#define CLKWHICH_HOSTCLK	6U
+ * Various Vin device table versions that are supported
-#define CLKWHICH_DISPCLK	7U
+ */
-#define CLKWHICH_XCLK		12U
+#define NV2080_CTRL_CLK_VIN_DEVICES_DISABLED        (0x00000000U)
-#define CLKWHICH_XBAR2CLK	14U
+#define NV2080_CTRL_CLK_VIN_DEVICES_V10             (0x00000001U)
-#define CLKWHICH_SYS2CLK	15U
+#define NV2080_CTRL_CLK_VIN_DEVICES_V20             (0x00000002U)
-#define CLKWHICH_HUB2CLK	16U
+
-#define CLKWHICH_GPC2CLK	17U
+#define CTRL_CLK_CLK_DOMAIN_TYPE_3X                                  0x01U
-#define CLKWHICH_PWRCLK		19U
+#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED                            0x02U
-#define CLKWHICH_NVDCLK		20U
+#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG                             0x03U
-#define CLKWHICH_PCIEGENCLK	26U
+#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER                           0x04U
+#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE                            0x05U
+#define CTRL_CLK_CLK_DOMAIN_TYPE_30_PROG                             0x06U
+#define CTRL_CLK_CLK_DOMAIN_TYPE_35_MASTER                           0x07U
+#define CTRL_CLK_CLK_DOMAIN_TYPE_35_SLAVE                            0x08U
+#define CTRL_CLK_CLK_DOMAIN_TYPE_35_PROG                             0x09U
+
+#define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID     0xFFU
+#define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID                      0xFF
+
+#define CTRL_CLK_CLK_PROG_TYPE_3X                              0x00U
+#define CTRL_CLK_CLK_PROG_TYPE_1X                              0x01U
+#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER                       0x02U
+#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO                 0x03U
+#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE                 0x04U
+#define CTRL_CLK_CLK_PROG_TYPE_35                              0x05U
+#define CTRL_CLK_CLK_PROG_TYPE_35_MASTER                       0x06U
+#define CTRL_CLK_CLK_PROG_TYPE_35_MASTER_RATIO                 0x07U
+#define CTRL_CLK_CLK_PROG_TYPE_35_MASTER_TABLE                 0x08U
+#define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN                         255U
+
+/*!
+ * Enumeration of CLK_PROG source types.
+ */
+#define CTRL_CLK_PROG_1X_SOURCE_PLL                            0x00U
+#define CTRL_CLK_PROG_1X_SOURCE_ONE_SOURCE                     0x01U
+#define CTRL_CLK_PROG_1X_SOURCE_FLL                            0x02U
+#define CTRL_CLK_PROG_1X_SOURCE_INVALID                        255U
+
+#define CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES 4U
+#define CTRL_CLK_CLK_PROG_35_MASTER_SEC_VF_ENTRY_VOLTRAIL_MAX	1U
+#define CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES 6U
+
+#define CTRL_CLK_CLK_VF_POINT_IDX_INVALID                      255U
+
+#define CTRL_CLK_CLK_VF_POINT_TYPE_FREQ                         0x01U
+#define CTRL_CLK_CLK_VF_POINT_TYPE_VOLT                         0x02U
+#define CTRL_CLK_CLK_VF_POINT_TYPE_35                           0x03U
+#define CTRL_CLK_CLK_VF_POINT_TYPE_35_FREQ                      0x04U
+#define CTRL_CLK_CLK_VF_POINT_TYPE_35_VOLT                      0x05U
+#define CTRL_CLK_CLK_VF_POINT_TYPE_35_VOLT_SEC                  0x06U
+#define CTRL_CLK_CLK_VF_POINT_TYPE_UNKNOWN                      255U
+
+
+
+struct ctrl_clk_domain_control_35_prog_clk_mon {
+	u32 flags;
+	u32 low_threshold_override;
+	u32 high_threshold_override;
+};
+
+struct ctrl_clk_domain_info_35_prog_clk_mon {
+	u8 low_threshold_vfe_idx;
+	u8 high_threshold_vfe_idx;
+};
+
+struct ctrl_clk_clk_prog_1x_master_source_fll {
+	u32 base_vfsmooth_volt_uv;
+	u32 max_vf_ramprate;
+	u32 max_freq_stepsize_mhz;
+};
+
+union ctrl_clk_clk_prog_1x_master_source_data {
+	struct ctrl_clk_clk_prog_1x_master_source_fll fll;
+};
+
+struct ctrl_clk_clk_vf_point_info_freq {
+	u16 freq_mhz;
+};
+
+struct ctrl_clk_clk_vf_point_info_volt {
+	u32  sourceVoltageuV;
+	u8  vfGainVfeEquIdx;
+	u8  clkDomainIdx;
+};
+
+struct ctrl_clk_clk_prog_1x_master_vf_entry {
+	u8 vfe_idx;
+	u8 gain_vfe_idx;
+	u8 vf_point_idx_first;
+	u8 vf_point_idx_last;
+};
+
+struct ctrl_clk_clk_prog_35_master_sec_vf_entry {
+	u8 vfe_idx;
+	u8 dvco_offset_vfe_idx;
+	u8 vf_point_idx_first;
+	u8 vf_point_idx_last;
+};
+
+struct ctrl_clk_clk_prog_35_master_sec_vf_entry_voltrail {
+	struct ctrl_clk_clk_prog_35_master_sec_vf_entry sec_vf_entries[
+			CTRL_CLK_CLK_PROG_35_MASTER_SEC_VF_ENTRY_VOLTRAIL_MAX];
+};
+
+struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry {
+	u8 clk_dom_idx;
+	u8 ratio;
+};
+
+struct ctrl_clk_clk_prog_1x_master_table_slave_entry {
+	u8 clk_dom_idx;
+	u16 freq_mhz;
+};
+
+struct ctrl_clk_clk_prog_1x_source_pll {
+	u8 pll_idx;
+	u8 freq_step_size_mhz;
+};
+
+struct ctrl_clk_vin_v10 {
+	u32 slope;
+	u32 intercept;
+};
+
+struct ctrl_clk_vin_v20 {
+	s8 offset;
+	s8 gain;
+	u8 coarse_control;
+	u8 offset_vfe_idx;
+};
+
+union ctrl_clk_vin_data_v20 {
+	struct ctrl_clk_vin_v10 cal_v10;
+	struct ctrl_clk_vin_v20 cal_v20;
+};
+
+struct ctrl_clk_vin_device_info_data_v10 {
+	struct ctrl_clk_vin_v10 vin_cal;
+};
+
+struct ctrl_clk_vin_device_info_data_v20 {
+	u8 cal_type;
+	union ctrl_clk_vin_data_v20 vin_cal;
+};
+
+union ctrl_clk_clk_prog_1x_source_data {
+	struct ctrl_clk_clk_prog_1x_source_pll source_pll;
+};
+
+#define CTRL_CLK_CLK_VF_POINT_FREQ_TUPLE_MAX_SIZE		0x5U
+
+struct ctrl_clk_vf_point_freq_tuple {
+	u16 freqMHz;
+};
+
+struct ctrl_clk_vf_point_base_vf_tuple {
+	struct ctrl_clk_vf_point_freq_tuple
+		freqTuple[CTRL_CLK_CLK_VF_POINT_FREQ_TUPLE_MAX_SIZE];
+	u32 voltageuV;
+};
+
+#define CTRL_CLK_CLK_VF_POINT_DVCO_OFFSET_CODE_INVALID   0xFFU
+
+struct ctrl_clk_vf_point_base_vf_tuple_sec {
+	struct ctrl_clk_vf_point_base_vf_tuple  super;
+	u8 dvco_offset_code;
+};
+
+struct ctrl_clk_vf_point_vf_tuple {
+	u16 freqMHz;
+	u32 voltageuV;
+};
+
+struct ctrl_clk_vf_input {
+	u8 flags;
+	u32 value;
+};
+
+struct ctrl_clk_vf_output {
+	u32 input_best_match;
+	u32 value;
+};
+
+#define CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(pvfpair)                          \
+	((pvfpair)->freq_mhz)
+
+#define CTRL_CLK_VF_PAIR_VOLTAGE_UV_GET(pvfpair)                        \
+	((pvfpair)->voltage_uv)
+
+#define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz)                \
+	(((pvfpair)->freq_mhz) = (_freqmhz))
+
+#define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz)                \
+	(((pvfpair)->freq_mhz) = (_freqmhz))
+
+
+#define CTRL_CLK_VF_PAIR_VOLTAGE_UV_SET(pvfpair, _voltageuv)	        \
+	(((pvfpair)->voltage_uv) = (_voltageuv))
 
 #define NV_PMU_RPC_ID_CLK_CNTR_SAMPLE_DOMAIN                               0x01U
 #define NV_PMU_RPC_ID_CLK_CLK_DOMAIN_35_PROG_VOLT_TO_FREQ                  0x02U
@@ -292,17 +470,6 @@ union nv_pmu_clk_clk_prog_boardobj_set_union {
 
 NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_prog);
 
-struct nv_pmu_clk_lut_device_desc {
-	u8 vselect_mode;
-	u16 hysteresis_threshold;
-};
-
-struct nv_pmu_clk_regime_desc {
-	u8 regime_id;
-	u8 target_regime_id_override;
-	u16 fixed_freq_regime_limit_mhz;
-};
-
 struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header {
 	struct nv_pmu_boardobjgrp_e32 super;
 	struct ctrl_boardobjgrp_mask_e32 lut_prog_master_mask;
@@ -464,29 +631,6 @@ union nv_pmu_clk_clk_vf_point_boardobj_get_status_union {
 
 NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(clk, clk_vf_point);
 
-#define NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS                                 (12U)
-
-struct nv_pmu_clk_clk_domain_list {
-	u8 num_domains;
-	struct ctrl_clk_clk_domain_list_item clk_domains[
-		NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS];
-};
-
-struct nv_pmu_clk_clk_domain_list_v1 {
-	u8 num_domains;
-	struct ctrl_clk_clk_domain_list_item_v1 clk_domains[
-		NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS];
-};
-
-struct nv_pmu_clk_vf_change_inject {
-	u8 flags;
-	struct nv_pmu_clk_clk_domain_list clk_list;
-};
-
-struct nv_pmu_clk_vf_change_inject_v1 {
-	u8 flags;
-	struct nv_pmu_clk_clk_domain_list_v1 clk_list;
-};
 
 #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES      (0x00000001U)
 

drivers/gpu/nvgpu/common/pmu/fw/fw_ns_bootstrap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
 #include <nvgpu/dma.h>
 #include <nvgpu/firmware.h>
 #include <nvgpu/pmu/fw.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 static int pmu_prepare_ns_ucode_blob(struct gk20a *g)
 {

drivers/gpu/nvgpu/common/pmu/lsfm/lsfm_sw_gm20b.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,6 +27,7 @@
 #include <nvgpu/pmu/cmd.h>
 #include <nvgpu/pmu/lsfm.h>
 #include <nvgpu/pmu/fw.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 #include "lsfm_sw_gm20b.h"
 

drivers/gpu/nvgpu/common/pmu/perf/change_seq.c

@@ -24,7 +24,6 @@
 #include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/timers.h>
-#include <nvgpu/pmu/pmuif/ctrlclk.h>
 #include <nvgpu/boardobj.h>
 #include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/pmu/clk/clk.h>

drivers/gpu/nvgpu/common/pmu/perf/perf.c

@@ -24,6 +24,7 @@
 #include <nvgpu/pmu.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/clk_arb.h>
 #include <nvgpu/pmu/perf.h>
 #include <nvgpu/pmu/cmd.h>

drivers/gpu/nvgpu/common/pmu/perf/pstate.c

@@ -30,8 +30,8 @@
 #include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/boardobjgrp_e255.h>
 #include <nvgpu/pmu/boardobjgrp_classes.h>
-#include <nvgpu/pmu/perf.h>
 #include <nvgpu/pmu/clk/clk.h>
+#include <nvgpu/pmu/perf.h>
 
 #include "ucode_perf_pstate_inf.h"
 #include "pstate.h"

drivers/gpu/nvgpu/common/pmu/perf/ucode_perf_change_seq_inf.h

@@ -1,7 +1,7 @@
 /*
  * general p state infrastructure
  *
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -24,6 +24,7 @@
 #ifndef NVGPU_PMUIF_CTRLPERF_H
 #define NVGPU_PMUIF_CTRLPERF_H
 
+
 #define CTRL_PERF_CHANGE_SEQ_VERSION_35				0x04U
 
 /*!

drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c

@@ -28,8 +28,8 @@
 #include <nvgpu/boardobjgrpmask.h>
 #include <nvgpu/pmu/boardobjgrp_classes.h>
 #include <nvgpu/string.h>
-#include <nvgpu/pmu/perf.h>
 #include <nvgpu/pmu/clk/clk.h>
+#include <nvgpu/pmu/perf.h>
 #include <nvgpu/pmu/clk/clk_fll.h>
 #include <nvgpu/pmu/cmd.h>
 

drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c

@@ -25,6 +25,7 @@
 #include <nvgpu/boardobjgrp.h>
 #include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/pmu/boardobjgrp_classes.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/string.h>
 #include <nvgpu/pmu/perf.h>
 

drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h

@@ -25,7 +25,6 @@
 
 #include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
 #include <nvgpu/pmu/pmuif/boardobj.h>
-#include <nvgpu/pmu/pmuif/clk.h>
 #include <nvgpu/pmu/pmuif/cmn.h>
 #include <nvgpu/flcnif_cmn.h>
 
@@ -107,30 +106,6 @@ struct nv_pmu_super_surface {
 		 * member present above to know the offset of
 		 * required boardobj from super surface in nvgpu
 		 */
-		struct  {
-			struct nv_pmu_clk_clk_vin_device_boardobj_grp_set
-				clk_vin_device_grp_set;
-			struct nv_pmu_clk_clk_domain_boardobj_grp_set
-				clk_domain_grp_set;
-			struct nv_pmu_clk_clk_fll_device_boardobj_grp_set
-				clk_fll_device_grp_set;
-			struct nv_pmu_clk_clk_prog_boardobj_grp_set
-				clk_prog_grp_set;
-			struct nv_pmu_clk_clk_vf_point_boardobj_grp_set
-				clk_vf_point_grp_set;
-			struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status
-				clk_vin_device_grp_get_status;
-			struct nv_pmu_clk_clk_fll_device_boardobj_grp_get_status
-				clk_fll_device_grp_get_status;
-			struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status
-				clk_vf_point_grp_get_status;
-		} clk;
-		struct {
-			struct nv_pmu_clk_clk_vf_point_boardobj_grp_set
-				clk_vf_point_grp_set;
-			struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status
-				clk_vf_point_grp_get_status;
-		} clk_35;
 	};
 };
 

drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c

@@ -29,6 +29,7 @@
 #include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/pmu/boardobjgrp_classes.h>
 #include <nvgpu/string.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/perf.h>
 #include <nvgpu/pmu/volt.h>
 

drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c

@@ -26,6 +26,7 @@
 #include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/pmu/boardobjgrp_classes.h>
 #include <nvgpu/string.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/perf.h>
 
 #include "ucode_volt_inf.h"

drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c

@@ -26,6 +26,7 @@
 #include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/pmu/boardobjgrp_classes.h>
 #include <nvgpu/string.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/perf.h>
 #include <nvgpu/pmu/volt.h>
 

drivers/gpu/nvgpu/common/vgpu/clk_vgpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -24,6 +24,7 @@
 #include <nvgpu/vgpu/vgpu.h>
 #include <nvgpu/vgpu/vgpu_ivc.h>
 #include <nvgpu/clk_arb.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 #include "clk_vgpu.h"
 #include "common/vgpu/ivc/comm_vgpu.h"

drivers/gpu/nvgpu/hal/clk/clk_gm20b.c

@@ -1,7 +1,7 @@
 /*
  * GM20B Clocks
  *
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -33,7 +33,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/nvgpu_init.h>
 #include <nvgpu/therm.h>
-#include <nvgpu/pmu/pmuif/ctrlclk.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 #include "clk_gm20b.h"
 

drivers/gpu/nvgpu/hal/clk/clk_tu104.c

@@ -30,13 +30,12 @@
 #include <nvgpu/kmem.h>
 #include <nvgpu/io.h>
 #include <nvgpu/list.h>
-#include <nvgpu/clk_arb.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/soc.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/clk.h>
 #include <nvgpu/pmu/perf.h>
 #include <nvgpu/clk_arb.h>
-#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/clk/clk_domain.h>
 #include <nvgpu/pmu/volt.h>
 #include <nvgpu/hw/tu104/hw_trim_tu104.h>

drivers/gpu/nvgpu/hal/fuse/fuse_gp106.c

@@ -1,7 +1,7 @@
 /*
  * GP106 FUSE
  *
- * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
 #include <nvgpu/enabled.h>
 #include <nvgpu/io.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 #include "fuse_gp106.h"
 

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c

@@ -28,7 +28,6 @@
 #include <nvgpu/soc.h>
 #include <nvgpu/static_analysis.h>
 #include <nvgpu/gr/gr_utils.h>
-#include <nvgpu/pmu/pmuif/ctrlclk.h>
 
 #include "gr_falcon_gm20b.h"
 #include "common/gr/gr_falcon_priv.h"

drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c

@@ -28,7 +28,7 @@
 #include <nvgpu/soc.h>
 #include <nvgpu/static_analysis.h>
 #include <nvgpu/gr/gr_utils.h>
-#include <nvgpu/pmu/pmuif/ctrlclk.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 #include "gr_falcon_gm20b.h"
 #include "common/gr/gr_falcon_priv.h"

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -212,13 +212,13 @@
 #endif
 #include <nvgpu/gr/setup.h>
 #include <nvgpu/gr/fecs_trace.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/perf.h>
 #include <nvgpu/gr/gr_falcon.h>
 #include <nvgpu/gr/gr.h>
 #include <nvgpu/gr/gr_intr.h>
 #include <nvgpu/pmu/pmu_perfmon.h>
 #include <nvgpu/nvgpu_init.h>
-#include <nvgpu/pmu/clk/clk.h>
 
 #include <nvgpu/hw/tu104/hw_pwr_tu104.h>
 

drivers/gpu/nvgpu/include/nvgpu/clk_arb.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -37,7 +37,6 @@ struct gk20a;
 #include <nvgpu/cond.h>
 #include <nvgpu/boardobj.h>
 #include <nvgpu/boardobjgrp_e32.h>
-#include <nvgpu/pmu/pmuif/ctrlclk.h>
 #include <nvgpu/pmu/volt.h>
 
 #define MAX_F_POINTS 256

drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h

@@ -26,6 +26,101 @@
 #define NVGPU_PMU_CLK_H
 
 #include <nvgpu/types.h>
+#include <nvgpu/pmu/pmuif/ctrlboardobj.h>
+
+/*!
+ * Valid global VIN ID values
+ */
+#define	CTRL_CLK_VIN_ID_SYS		0x00000000U
+#define	CTRL_CLK_VIN_ID_LTC		0x00000001U
+#define	CTRL_CLK_VIN_ID_XBAR		0x00000002U
+#define	CTRL_CLK_VIN_ID_GPC0		0x00000003U
+#define	CTRL_CLK_VIN_ID_GPC1		0x00000004U
+#define	CTRL_CLK_VIN_ID_GPC2		0x00000005U
+#define	CTRL_CLK_VIN_ID_GPC3		0x00000006U
+#define	CTRL_CLK_VIN_ID_GPC4		0x00000007U
+#define	CTRL_CLK_VIN_ID_GPC5		0x00000008U
+#define	CTRL_CLK_VIN_ID_GPCS		0x00000009U
+#define	CTRL_CLK_VIN_ID_SRAM		0x0000000AU
+#define	CTRL_CLK_VIN_ID_UNDEFINED	0x000000FFU
+
+#define	CTRL_CLK_VIN_TYPE_DISABLED 0x00000000U
+#define CTRL_CLK_VIN_TYPE_V20      0x00000002U
+
+/* valid clock domain values */
+#define CTRL_CLK_DOMAIN_MCLK                                (0x00000010U)
+#define CTRL_CLK_DOMAIN_HOSTCLK                             (0x00000020U)
+#define CTRL_CLK_DOMAIN_DISPCLK                             (0x00000040U)
+#define CTRL_CLK_DOMAIN_GPC2CLK                             (0x00010000U)
+#define CTRL_CLK_DOMAIN_XBAR2CLK                            (0x00040000U)
+#define CTRL_CLK_DOMAIN_SYS2CLK                             (0x00800000U)
+#define CTRL_CLK_DOMAIN_HUB2CLK                             (0x01000000U)
+#define CTRL_CLK_DOMAIN_UTILSCLK                            (0x00040000U)
+#define CTRL_CLK_DOMAIN_PWRCLK                              (0x00080000U)
+#define CTRL_CLK_DOMAIN_NVDCLK                              (0x00100000U)
+#define CTRL_CLK_DOMAIN_PCIEGENCLK                          (0x00200000U)
+#define CTRL_CLK_DOMAIN_XCLK                                (0x04000000U)
+#define CTRL_CLK_DOMAIN_NVL_COMMON                          (0x08000000U)
+#define CTRL_CLK_DOMAIN_PEX_REFCLK                          (0x10000000U)
+
+#define CTRL_CLK_DOMAIN_GPCCLK                              (0x00000001U)
+#define CTRL_CLK_DOMAIN_XBARCLK                             (0x00000002U)
+#define CTRL_CLK_DOMAIN_SYSCLK                              (0x00000004U)
+#define CTRL_CLK_DOMAIN_HUBCLK                              (0x00000008U)
+
+
+#define CTRL_CLK_FLL_REGIME_ID_INVALID                     ((u8)0x00000000)
+#define CTRL_CLK_FLL_REGIME_ID_FFR                         ((u8)0x00000001)
+#define CTRL_CLK_FLL_REGIME_ID_FR                          ((u8)0x00000002)
+
+#define CTRL_CLK_CLK_DOMAIN_CLIENT_MAX_DOMAINS			16
+#define CLK_CLOCK_MON_DOMAIN_COUNT				0x32U
+#define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 4U
+/*
+ *  Try to get gpc2clk, mclk, sys2clk, xbar2clk work for Pascal
+ *
+ *  mclk is same for both
+ *  gpc2clk is 17 for Pascal and 13 for Volta, making it 17
+ *    as volta uses gpcclk
+ *  sys2clk is 20 in Pascal and 15 in Volta.
+ *    Changing for Pascal would break nvdclk of Volta
+ *  xbar2clk is 19 in Pascal and 14 in Volta
+ *    Changing for Pascal would break pwrclk of Volta
+ */
+#define CLKWHICH_GPCCLK		1U
+#define CLKWHICH_XBARCLK	2U
+#define CLKWHICH_SYSCLK		3U
+#define CLKWHICH_HUBCLK		4U
+#define CLKWHICH_MCLK		5U
+#define CLKWHICH_HOSTCLK	6U
+#define CLKWHICH_DISPCLK	7U
+#define CLKWHICH_XCLK		12U
+#define CLKWHICH_XBAR2CLK	14U
+#define CLKWHICH_SYS2CLK	15U
+#define CLKWHICH_HUB2CLK	16U
+#define CLKWHICH_GPC2CLK	17U
+#define CLKWHICH_PWRCLK		19U
+#define CLKWHICH_NVDCLK		20U
+#define CLKWHICH_PCIEGENCLK	26U
+
+
+/*!
+ * Mask of all GPC VIN IDs supported by RM
+ */
+#define CTRL_CLK_LUT_NUM_ENTRIES_MAX   (128U)
+#define CTRL_CLK_LUT_NUM_ENTRIES_GV10x (128U)
+#define CTRL_CLK_LUT_NUM_ENTRIES_GP10x (100U)
+#define CTRL_CLK_VIN_STEP_SIZE_UV (6250U)
+#define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000U)
+#define CTRL_CLK_FLL_TYPE_DISABLED 0U
+
+#define CTRL_CLK_FLL_LUT_VSELECT_LOGIC			   (0x00000000U)
+#define CTRL_CLK_FLL_LUT_VSELECT_MIN			   (0x00000001U)
+#define CTRL_CLK_FLL_LUT_VSELECT_SRAM			   (0x00000002U)
+
+#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_HW_REQ  (0x00000000U)
+#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_MIN     (0x00000001U)
+#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_SW_REQ  (0x00000003U)
 
 struct gk20a;
 struct nvgpu_avfsfllobjs;
@@ -36,11 +131,86 @@ struct nvgpu_clk_mclk_state;
 struct nvgpu_clk_slave_freq;
 struct ctrl_perf_change_seq_change_input;
 
-struct nvgpu_clockentry {
+
-	u8 vbios_clk_domain;
+struct ctrl_clk_domain_clk_mon_item {
-	u8 clk_which;
+	u32 clk_api_domain;
-	u8 perf_index;
+	u32 clk_freq_Mhz;
-	u32 api_clk_domain;
+	u32 low_threshold_percentage;
+	u32 high_threshold_percentage;
+};
+
+struct ctrl_clk_domain_clk_mon_list {
+	u8 num_domain;
+	struct ctrl_clk_domain_clk_mon_item
+		clk_domain[CTRL_CLK_CLK_DOMAIN_CLIENT_MAX_DOMAINS];
+};
+
+struct ctrl_clk_clk_domain_list_item_v1 {
+	u32  clk_domain;
+	u32  clk_freq_khz;
+	u8   regime_id;
+	u8   source;
+};
+
+struct ctrl_clk_clk_domain_list {
+	u8 num_domains;
+	struct ctrl_clk_clk_domain_list_item_v1
+		clk_domains[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
+};
+
+struct clk_domain_mon_status {
+	u32 clk_api_domain;
+	u32 low_threshold;
+	u32 high_threshold;
+	u32 clk_domain_fault_status;
+};
+
+struct clk_domains_mon_status_params {
+	u32 clk_mon_domain_mask;
+	struct clk_domain_mon_status
+		clk_mon_list[CLK_CLOCK_MON_DOMAIN_COUNT];
+};
+
+struct ctrl_clk_vin_sw_override_list_item {
+	u8 override_mode;
+	u32 voltage_uV;
+};
+
+struct ctrl_clk_vin_sw_override_list {
+	struct ctrl_boardobjgrp_mask_e32 volt_rails_mask;
+	struct ctrl_clk_vin_sw_override_list_item
+		volt[4];
+};
+
+union ctrl_clk_freq_delta_data {
+	s32 delta_khz;
+	s16 delta_percent;
+};
+struct ctrl_clk_freq_delta {
+	u8 type;
+	union ctrl_clk_freq_delta_data data;
+};
+
+struct ctrl_clk_clk_delta {
+	struct ctrl_clk_freq_delta freq_delta;
+	int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS];
+};
+
+struct nv_pmu_clk_lut_device_desc {
+	u8 vselect_mode;
+	u16 hysteresis_threshold;
+};
+
+
+struct nv_pmu_clk_regime_desc {
+	u8 regime_id;
+	u8 target_regime_id_override;
+	u16 fixed_freq_regime_limit_mhz;
+};
+
+struct ctrl_clk_vf_pair {
+	u16 freq_mhz;
+	u32 voltage_uv;
 };
 
 struct nvgpu_set_fll_clk {

drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h

@@ -27,7 +27,6 @@
 
 #include <nvgpu/types.h>
 #include <nvgpu/boardobjgrpmask.h>
-#include <nvgpu/pmu/pmuif/clk.h>
 
 struct gk20a;
 struct fll_device;

drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h

@@ -27,7 +27,6 @@
 #include <nvgpu/pmu/pmuif/pg.h>
 #include <nvgpu/pmu/pmuif/acr.h>
 #include <nvgpu/pmu/pmuif/boardobj.h>
-#include <nvgpu/pmu/pmuif/clk.h>
 #include <nvgpu/pmu/pmuif/pmgr.h>
 #include <nvgpu/pmu/pmuif/rpc.h>
 
@@ -49,7 +48,6 @@ struct pmu_cmd {
 		struct pmu_zbc_cmd zbc;
 		struct pmu_acr_cmd acr;
 		struct nv_pmu_boardobj_cmd boardobj;
-		struct nv_pmu_clk_cmd clk;
 		struct nv_pmu_pmgr_cmd pmgr;
 		struct nv_pmu_rpc_cmd rpc;
 	} cmd;

drivers/gpu/nvgpu/include/nvgpu/pmu/msg.h

@@ -29,7 +29,6 @@
 #include <nvgpu/pmu/pmuif/acr.h>
 #include <nvgpu/pmu/pmuif/rpc.h>
 #include <nvgpu/pmu/pmuif/boardobj.h>
-#include <nvgpu/pmu/pmuif/clk.h>
 #include <nvgpu/pmu/pmuif/pmgr.h>
 
 /* GPU ID */
@@ -68,7 +67,6 @@ struct pmu_msg {
 			struct pmu_rc_msg rc;
 			struct pmu_acr_msg acr;
 			struct nv_pmu_boardobj_msg boardobj;
-			struct nv_pmu_clk_msg clk;
 			struct nv_pmu_pmgr_msg pmgr;
 			struct nv_pmu_rpc_msg rpc;
 		} msg;

drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlclk.h

@@ -1,313 +0,0 @@
-/*
- * general p state infrastructure
- *
- * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef NVGPU_PMUIF_CTRLCLK_H
-#define NVGPU_PMUIF_CTRLCLK_H
-
-#include "ctrlboardobj.h"
-#include "ctrlclkavfs.h"
-
-#define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 4U
-
-/* valid clock domain values */
-#define CTRL_CLK_DOMAIN_MCLK                                (0x00000010U)
-#define CTRL_CLK_DOMAIN_HOSTCLK                             (0x00000020U)
-#define CTRL_CLK_DOMAIN_DISPCLK                             (0x00000040U)
-#define CTRL_CLK_DOMAIN_GPC2CLK                             (0x00010000U)
-#define CTRL_CLK_DOMAIN_XBAR2CLK                            (0x00040000U)
-#define CTRL_CLK_DOMAIN_SYS2CLK                             (0x00800000U)
-#define CTRL_CLK_DOMAIN_HUB2CLK                             (0x01000000U)
-#define CTRL_CLK_DOMAIN_UTILSCLK                            (0x00040000U)
-#define CTRL_CLK_DOMAIN_PWRCLK                              (0x00080000U)
-#define CTRL_CLK_DOMAIN_NVDCLK                              (0x00100000U)
-#define CTRL_CLK_DOMAIN_PCIEGENCLK                          (0x00200000U)
-#define CTRL_CLK_DOMAIN_XCLK                                (0x04000000U)
-#define CTRL_CLK_DOMAIN_NVL_COMMON                          (0x08000000U)
-#define CTRL_CLK_DOMAIN_PEX_REFCLK                          (0x10000000U)
-
-#define CTRL_CLK_DOMAIN_GPCCLK                              (0x00000001U)
-#define CTRL_CLK_DOMAIN_XBARCLK                             (0x00000002U)
-#define CTRL_CLK_DOMAIN_SYSCLK                              (0x00000004U)
-#define CTRL_CLK_DOMAIN_HUBCLK                              (0x00000008U)
-
-#define CTRL_CLK_CLK_DOMAIN_TYPE_3X                                  0x01U
-#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED                            0x02U
-#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG                             0x03U
-#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER                           0x04U
-#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE                            0x05U
-#define CTRL_CLK_CLK_DOMAIN_TYPE_30_PROG                             0x06U
-#define CTRL_CLK_CLK_DOMAIN_TYPE_35_MASTER                           0x07U
-#define CTRL_CLK_CLK_DOMAIN_TYPE_35_SLAVE                            0x08U
-#define CTRL_CLK_CLK_DOMAIN_TYPE_35_PROG                             0x09U
-
-#define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID     0xFFU
-#define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID                      0xFF
-
-#define CTRL_CLK_CLK_PROG_TYPE_3X                              0x00U
-#define CTRL_CLK_CLK_PROG_TYPE_1X                              0x01U
-#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER                       0x02U
-#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO                 0x03U
-#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE                 0x04U
-#define CTRL_CLK_CLK_PROG_TYPE_35                              0x05U
-#define CTRL_CLK_CLK_PROG_TYPE_35_MASTER                       0x06U
-#define CTRL_CLK_CLK_PROG_TYPE_35_MASTER_RATIO                 0x07U
-#define CTRL_CLK_CLK_PROG_TYPE_35_MASTER_TABLE                 0x08U
-#define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN                         255U
-
-/*!
- * Enumeration of CLK_PROG source types.
- */
-#define CTRL_CLK_PROG_1X_SOURCE_PLL                            0x00U
-#define CTRL_CLK_PROG_1X_SOURCE_ONE_SOURCE                     0x01U
-#define CTRL_CLK_PROG_1X_SOURCE_FLL                            0x02U
-#define CTRL_CLK_PROG_1X_SOURCE_INVALID                        255U
-
-#define CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES 4U
-#define CTRL_CLK_CLK_PROG_35_MASTER_SEC_VF_ENTRY_VOLTRAIL_MAX	1U
-#define CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES 6U
-
-#define CTRL_CLK_CLK_VF_POINT_IDX_INVALID                      255U
-
-#define CTRL_CLK_CLK_VF_POINT_TYPE_FREQ                         0x01U
-#define CTRL_CLK_CLK_VF_POINT_TYPE_VOLT                         0x02U
-#define CTRL_CLK_CLK_VF_POINT_TYPE_35                           0x03U
-#define CTRL_CLK_CLK_VF_POINT_TYPE_35_FREQ                      0x04U
-#define CTRL_CLK_CLK_VF_POINT_TYPE_35_VOLT                      0x05U
-#define CTRL_CLK_CLK_VF_POINT_TYPE_35_VOLT_SEC                  0x06U
-#define CTRL_CLK_CLK_VF_POINT_TYPE_UNKNOWN                      255U
-
-#define CTRL_CLK_CLK_DOMAIN_CLIENT_MAX_DOMAINS			16
-#define CLK_CLOCK_MON_DOMAIN_COUNT				0x32U
-
-struct ctrl_clk_domain_control_35_prog_clk_mon {
-	u32 flags;
-	u32 low_threshold_override;
-	u32 high_threshold_override;
-};
-
-struct ctrl_clk_domain_info_35_prog_clk_mon {
-	u8 low_threshold_vfe_idx;
-	u8 high_threshold_vfe_idx;
-};
-
-struct ctrl_clk_clk_prog_1x_master_source_fll {
-	u32 base_vfsmooth_volt_uv;
-	u32 max_vf_ramprate;
-	u32 max_freq_stepsize_mhz;
-};
-
-union ctrl_clk_clk_prog_1x_master_source_data {
-	struct ctrl_clk_clk_prog_1x_master_source_fll fll;
-};
-
-struct ctrl_clk_clk_vf_point_info_freq {
-	u16 freq_mhz;
-};
-
-struct ctrl_clk_clk_vf_point_info_volt {
-	u32  sourceVoltageuV;
-	u8  vfGainVfeEquIdx;
-	u8  clkDomainIdx;
-};
-
-struct ctrl_clk_clk_prog_1x_master_vf_entry {
-	u8 vfe_idx;
-	u8 gain_vfe_idx;
-	u8 vf_point_idx_first;
-	u8 vf_point_idx_last;
-};
-
-struct ctrl_clk_clk_prog_35_master_sec_vf_entry {
-	u8 vfe_idx;
-	u8 dvco_offset_vfe_idx;
-	u8 vf_point_idx_first;
-	u8 vf_point_idx_last;
-};
-
-struct ctrl_clk_clk_prog_35_master_sec_vf_entry_voltrail {
-	struct ctrl_clk_clk_prog_35_master_sec_vf_entry sec_vf_entries[
-			CTRL_CLK_CLK_PROG_35_MASTER_SEC_VF_ENTRY_VOLTRAIL_MAX];
-};
-
-struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry {
-	u8 clk_dom_idx;
-	u8 ratio;
-};
-
-struct ctrl_clk_clk_prog_1x_master_table_slave_entry {
-	u8 clk_dom_idx;
-	u16 freq_mhz;
-};
-
-struct ctrl_clk_clk_prog_1x_source_pll {
-	u8 pll_idx;
-	u8 freq_step_size_mhz;
-};
-
-union ctrl_clk_freq_delta_data {
-	s32 delta_khz;
-	s16 delta_percent;
-};
-struct ctrl_clk_freq_delta {
-	u8 type;
-	union ctrl_clk_freq_delta_data data;
-};
-
-struct ctrl_clk_clk_delta {
-	struct ctrl_clk_freq_delta freq_delta;
-	int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS];
-};
-
-struct ctrl_clk_vin_v10 {
-	u32 slope;
-	u32 intercept;
-};
-
-struct ctrl_clk_vin_v20 {
-	s8 offset;
-	s8 gain;
-	u8 coarse_control;
-	u8 offset_vfe_idx;
-};
-
-union ctrl_clk_vin_data_v20 {
-	struct ctrl_clk_vin_v10 cal_v10;
-	struct ctrl_clk_vin_v20 cal_v20;
-};
-
-struct ctrl_clk_vin_device_info_data_v10 {
-	struct ctrl_clk_vin_v10 vin_cal;
-};
-
-struct ctrl_clk_vin_device_info_data_v20 {
-	u8 cal_type;
-	union ctrl_clk_vin_data_v20 vin_cal;
-};
-
-union ctrl_clk_clk_prog_1x_source_data {
-	struct ctrl_clk_clk_prog_1x_source_pll source_pll;
-};
-
-struct ctrl_clk_vf_pair {
-	u16 freq_mhz;
-	u32 voltage_uv;
-};
-
-#define CTRL_CLK_CLK_VF_POINT_FREQ_TUPLE_MAX_SIZE		0x5U
-
-struct ctrl_clk_vf_point_freq_tuple {
-	u16 freqMHz;
-};
-
-struct ctrl_clk_vf_point_base_vf_tuple {
-	struct ctrl_clk_vf_point_freq_tuple
-		freqTuple[CTRL_CLK_CLK_VF_POINT_FREQ_TUPLE_MAX_SIZE];
-	u32 voltageuV;
-};
-
-#define CTRL_CLK_CLK_VF_POINT_DVCO_OFFSET_CODE_INVALID   0xFFU
-
-struct ctrl_clk_vf_point_base_vf_tuple_sec {
-	struct ctrl_clk_vf_point_base_vf_tuple  super;
-	u8 dvco_offset_code;
-};
-
-struct ctrl_clk_vf_point_vf_tuple {
-	u16 freqMHz;
-	u32 voltageuV;
-};
-
-struct ctrl_clk_vf_input {
-	u8 flags;
-	u32 value;
-};
-
-struct ctrl_clk_vf_output {
-	u32 input_best_match;
-	u32 value;
-};
-
-struct ctrl_clk_clk_domain_list_item {
-	u32  clk_domain;
-	u32  clk_freq_khz;
-	u32  clk_flags;
-	u8   current_regime_id;
-	u8   target_regime_id;
-};
-
-struct ctrl_clk_clk_domain_list_item_v1 {
-	u32  clk_domain;
-	u32  clk_freq_khz;
-	u8   regime_id;
-	u8   source;
-};
-
-struct ctrl_clk_clk_domain_list {
-	u8 num_domains;
-	struct ctrl_clk_clk_domain_list_item_v1
-		clk_domains[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
-};
-
-struct ctrl_clk_domain_clk_mon_item {
-	u32 clk_api_domain;
-	u32 clk_freq_Mhz;
-	u32 low_threshold_percentage;
-	u32 high_threshold_percentage;
-};
-
-struct ctrl_clk_domain_clk_mon_list {
-	u8 num_domain;
-	struct ctrl_clk_domain_clk_mon_item
-		clk_domain[CTRL_CLK_CLK_DOMAIN_CLIENT_MAX_DOMAINS];
-};
-
-struct clk_domain_mon_status {
-	u32 clk_api_domain;
-	u32 low_threshold;
-	u32 high_threshold;
-	u32 clk_domain_fault_status;
-};
-
-struct clk_domains_mon_status_params {
-	u32 clk_mon_domain_mask;
-	struct clk_domain_mon_status
-		clk_mon_list[CLK_CLOCK_MON_DOMAIN_COUNT];
-};
-
-#define CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(pvfpair)                          \
-	((pvfpair)->freq_mhz)
-
-#define CTRL_CLK_VF_PAIR_VOLTAGE_UV_GET(pvfpair)                        \
-	((pvfpair)->voltage_uv)
-
-#define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz)                \
-	(((pvfpair)->freq_mhz) = (_freqmhz))
-
-#define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz)                \
-	(((pvfpair)->freq_mhz) = (_freqmhz))
-
-
-#define CTRL_CLK_VF_PAIR_VOLTAGE_UV_SET(pvfpair, _voltageuv)	        \
-	(((pvfpair)->voltage_uv) = (_voltageuv))
-
-#endif /* NVGPU_PMUIF_CTRLCLK_H */

drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlclkavfs.h

@@ -1,92 +0,0 @@
-/*
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef NVGPU_PMUIF_CTRLCLKAVFS_H
-#define NVGPU_PMUIF_CTRLCLKAVFS_H
-
-/*!
- * Valid global VIN ID values
- */
-#define	CTRL_CLK_VIN_ID_SYS		0x00000000U
-#define	CTRL_CLK_VIN_ID_LTC		0x00000001U
-#define	CTRL_CLK_VIN_ID_XBAR		0x00000002U
-#define	CTRL_CLK_VIN_ID_GPC0		0x00000003U
-#define	CTRL_CLK_VIN_ID_GPC1		0x00000004U
-#define	CTRL_CLK_VIN_ID_GPC2		0x00000005U
-#define	CTRL_CLK_VIN_ID_GPC3		0x00000006U
-#define	CTRL_CLK_VIN_ID_GPC4		0x00000007U
-#define	CTRL_CLK_VIN_ID_GPC5		0x00000008U
-#define	CTRL_CLK_VIN_ID_GPCS		0x00000009U
-#define	CTRL_CLK_VIN_ID_SRAM		0x0000000AU
-#define	CTRL_CLK_VIN_ID_UNDEFINED	0x000000FFU
-
-#define	CTRL_CLK_VIN_TYPE_DISABLED 0x00000000U
-#define CTRL_CLK_VIN_TYPE_V20      0x00000002U
-
-/*!
- * Various types of VIN calibration that the GPU can support
- */
-#define CTRL_CLK_VIN_CAL_TYPE_V20           (0x00000001U)
-
-#define CTRL_CLK_VIN_VFE_IDX_INVALID		(0xFFU)
-
-/*!
- * Various Vin device table versions that are supported
- */
-#define NV2080_CTRL_CLK_VIN_DEVICES_DISABLED        (0x00000000U)
-#define NV2080_CTRL_CLK_VIN_DEVICES_V10             (0x00000001U)
-#define NV2080_CTRL_CLK_VIN_DEVICES_V20             (0x00000002U)
-
-/*!
- * Mask of all GPC VIN IDs supported by RM
- */
-#define CTRL_CLK_LUT_NUM_ENTRIES_MAX   (128U)
-#define CTRL_CLK_LUT_NUM_ENTRIES_GV10x (128U)
-#define CTRL_CLK_LUT_NUM_ENTRIES_GP10x (100U)
-#define CTRL_CLK_VIN_STEP_SIZE_UV (6250U)
-#define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000U)
-#define CTRL_CLK_FLL_TYPE_DISABLED 0U
-
-#define CTRL_CLK_FLL_REGIME_ID_INVALID                     ((u8)0x00000000)
-#define CTRL_CLK_FLL_REGIME_ID_FFR                         ((u8)0x00000001)
-#define CTRL_CLK_FLL_REGIME_ID_FR                          ((u8)0x00000002)
-
-#define CTRL_CLK_FLL_LUT_VSELECT_LOGIC			   (0x00000000U)
-#define CTRL_CLK_FLL_LUT_VSELECT_MIN			   (0x00000001U)
-#define CTRL_CLK_FLL_LUT_VSELECT_SRAM			   (0x00000002U)
-
-#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_HW_REQ  (0x00000000U)
-#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_MIN     (0x00000001U)
-#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_SW_REQ  (0x00000003U)
-
-struct ctrl_clk_vin_sw_override_list_item {
-	u8 override_mode;
-	u32 voltage_uV;
-};
-
-struct ctrl_clk_vin_sw_override_list {
-	struct ctrl_boardobjgrp_mask_e32 volt_rails_mask;
-	struct ctrl_clk_vin_sw_override_list_item
-		volt[4];
-};
-
-#endif /* NVGPU_PMUIF_CTRLCLKAVFS_H */

drivers/gpu/nvgpu/os/linux/clk.c

@@ -1,7 +1,7 @@
 /*
  * Linux clock support
  *
- * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -20,6 +20,7 @@
 
 #include <soc/tegra/tegra-dvfs.h>
 #include <soc/tegra/tegra-bpmp-dvfs.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 #include "clk.h"
 #include "os_linux.h"

drivers/gpu/nvgpu/os/linux/debug_clk_gm20b.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2019 NVIDIA Corporation.  All rights reserved.
+ * Copyright (C) 2017-2020 NVIDIA Corporation.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -18,6 +18,7 @@
 
 #include <nvgpu/io.h>
 #include <nvgpu/clk_arb.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 #include "hal/clk/clk_gm20b.h"
 #include "os_linux.h"

drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c

@@ -23,9 +23,9 @@
 #include <nvgpu/boardobj.h>
 #include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/boardobjgrp_e255.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/clk/clk_vf_point.h>
 #include <nvgpu/pmu/clk/clk_fll.h>
-#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/volt.h>
 
 #include "hal/clk/clk_tu104.h"

drivers/gpu/nvgpu/os/linux/debug_s_param.c

@@ -18,6 +18,7 @@
 #include "os_linux.h"
 #include "include/nvgpu/bios.h"
 
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/perf.h>
 
 static int get_s_param_info(void *data, u64 *val)

drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -40,6 +40,7 @@
 #include <nvgpu/pmu/pmu_pstate.h>
 #include <nvgpu/pmu/volt.h>
 #include <nvgpu/pmu/lpwr.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 #ifdef CONFIG_DEBUG_FS
 #include "os_linux.h"

drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c

@@ -20,6 +20,7 @@
 #include <linux/anon_inodes.h>
 #include <linux/fs.h>
 #include <uapi/linux/nvgpu.h>
+#include <nvgpu/pmu/clk/clk.h>
 
 #include <nvgpu/bitops.h>
 #include <nvgpu/kmem.h>

drivers/gpu/nvgpu/os/linux/scale.c

@@ -1,7 +1,7 @@
 /*
  * gk20a clock scaling profile
  *
- * Copyright (c) 2013-2019, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2013-2020, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -26,6 +26,7 @@
 #include <nvgpu/kmem.h>
 #include <nvgpu/log.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/clk_arb.h>
 #include <nvgpu/pmu/pmu_perfmon.h>
 

userspace/units/fuse/nvgpu-fuse-tu104.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,7 +27,8 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/fuse.h>
 #include <nvgpu/hal_init.h>
-#include <nvgpu/pmu/pmuif/ctrlclk.h>
+#include <nvgpu/pmu/clk/clk.h>
+
 #include "hal/fuse/fuse_gm20b.h"
 
 #include "nvgpu-fuse-priv.h"