diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h index a1eedc280..47226aa1a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h @@ -26,16 +26,16 @@ #include "ctrl/ctrlboardobj.h" /* board object group command id's. */ -#define NV_PMU_BOARDOBJGRP_CMD_SET 0x00 -#define NV_PMU_BOARDOBJGRP_CMD_GET_STATUS 0x01 +#define NV_PMU_BOARDOBJGRP_CMD_SET 0x00U +#define NV_PMU_BOARDOBJGRP_CMD_GET_STATUS 0x01U -#define NV_PMU_RPC_ID_CLK_BOARD_OBJ_GRP_CMD 0x00 -#define NV_PMU_RPC_ID_FAN_BOARD_OBJ_GRP_CMD 0x00 -#define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00 -#define NV_PMU_RPC_ID_PERF_CF_BOARD_OBJ_GRP_CMD 0x00 -#define NV_PMU_RPC_ID_PMGR_BOARD_OBJ_GRP_CMD 0x00 -#define NV_PMU_RPC_ID_THERM_BOARD_OBJ_GRP_CMD 0x00 -#define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00 +#define NV_PMU_RPC_ID_CLK_BOARD_OBJ_GRP_CMD 0x00U +#define NV_PMU_RPC_ID_FAN_BOARD_OBJ_GRP_CMD 0x00U +#define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00U +#define NV_PMU_RPC_ID_PERF_CF_BOARD_OBJ_GRP_CMD 0x00U +#define NV_PMU_RPC_ID_PMGR_BOARD_OBJ_GRP_CMD 0x00U +#define NV_PMU_RPC_ID_THERM_BOARD_OBJ_GRP_CMD 0x00U +#define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00U /* * Base structure describing a BOARDOBJ for communication between Kernel and diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h index f7157ee9c..70b93e12b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h @@ -30,31 +30,31 @@ * argument for communications between Kernel and PMU via the various generic * BOARDOBJGRP interfaces. */ -#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR 0x00 -#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU 0x01 +#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR 0x00U +#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU 0x01U -#define NV_PMU_PERF_CMD_ID_RPC (0x00000002) -#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003) -#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004) +#define NV_PMU_PERF_CMD_ID_RPC (0x00000002U) +#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003U) +#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004U) /*! * RPC calls serviced by PERF unit. */ -#define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00 -#define NV_PMU_RPC_ID_PERF_LOAD 0x01 -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_GET 0x02 -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_SET 0x03 -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_SET_CONTROL 0x04 -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUEUE_CHANGE 0x05 -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOCK 0x06 -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOAD 0x07 -#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUERY 0x08 -#define NV_PMU_RPC_ID_PERF_PERF_LIMITS_INVALIDATE 0x09 -#define NV_PMU_RPC_ID_PERF_VFE_EQU_EVAL 0x0A -#define NV_PMU_RPC_ID_PERF_VFE_INVALIDATE 0x0B -#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_SET 0x0C -#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_GET 0x0D -#define NV_PMU_RPC_ID_PERF__COUNT 0x0E +#define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00U +#define NV_PMU_RPC_ID_PERF_LOAD 0x01U +#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_GET 0x02U +#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_SET 0x03U +#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_SET_CONTROL 0x04U +#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUEUE_CHANGE 0x05U +#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOCK 0x06U +#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOAD 0x07U +#define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUERY 0x08U +#define NV_PMU_RPC_ID_PERF_PERF_LIMITS_INVALIDATE 0x09U +#define NV_PMU_RPC_ID_PERF_VFE_EQU_EVAL 0x0AU +#define NV_PMU_RPC_ID_PERF_VFE_INVALIDATE 0x0BU +#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_SET 0x0CU +#define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_GET 0x0DU +#define NV_PMU_RPC_ID_PERF__COUNT 0x0EU /* * Defines the structure that holds data * used to execute LOAD RPC. @@ -76,7 +76,7 @@ struct nv_pmu_perf_cmd_set_object { (offsetof(struct nv_pmu_perf_cmd_set_object, object)) /* RPC IDs */ -#define NV_PMU_PERF_RPC_ID_VFE_LOAD (0x00000001) +#define NV_PMU_PERF_RPC_ID_VFE_LOAD (0x00000001U) /*! * Command requesting execution of the perf RPC. @@ -121,10 +121,10 @@ struct nv_pmu_perf_rpc { /* PERF Message-type Definitions */ -#define NV_PMU_PERF_MSG_ID_RPC (0x00000003) -#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004) -#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006) -#define NV_PMU_PERF_MSG_ID_VFE_CALLBACK (0x00000005) +#define NV_PMU_PERF_MSG_ID_RPC (0x00000003U) +#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004U) +#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006U) +#define NV_PMU_PERF_MSG_ID_VFE_CALLBACK (0x00000005U) /*! * Message carrying the result of the perf RPC execution. diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h index 83f9ac1e3..a0e6c82c7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h @@ -35,7 +35,7 @@ struct nv_pmu_pmgr_i2c_device_desc { u8 i2c_port; }; -#define NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES (32) +#define NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES (32U) struct nv_pmu_pmgr_i2c_device_desc_table { u32 dev_mask; @@ -48,7 +48,7 @@ struct nv_pmu_pmgr_pwr_device_desc { u32 power_corr_factor; }; -#define NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM 0x03 +#define NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM 0x03U struct nv_pmu_pmgr_pwr_device_desc_ina3221 { struct nv_pmu_pmgr_pwr_device_desc super; @@ -105,9 +105,9 @@ struct nv_pmu_pmgr_pwr_channel { u32 dependent_ch_mask; }; -#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS 16 +#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS 16U -#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS 16 +#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS 16U struct nv_pmu_pmgr_pwr_channel_sensor { struct nv_pmu_pmgr_pwr_channel super; @@ -126,7 +126,7 @@ union nv_pmu_pmgr_pwr_channel_union { struct nv_pmu_pmgr_pwr_channel_pmu_compactible pmu_pwr_channel; }; -#define NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING 0x02 +#define NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING 0x02U struct nv_pmu_pmgr_pwr_monitor_pstate { u32 hw_channel_mask; @@ -193,9 +193,9 @@ struct nv_pmu_pmgr_pwr_monitor_pack { struct nv_pmu_pmgr_pwr_chrelationship_desc ch_rels; }; -#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES 32 +#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES 32U -#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS 32 +#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS 32U struct nv_pmu_pmgr_pwr_policy { struct nv_pmu_boardobj super; @@ -258,21 +258,21 @@ union nv_pmu_pmgr_pwr_violation_union { struct nv_pmu_pmgr_pwr_violation_pmu_compactible violation; }; -#define NV_PMU_PMGR_PWR_POLICY_DESC_TABLE_VERSION_3X 0x30 +#define NV_PMU_PMGR_PWR_POLICY_DESC_TABLE_VERSION_3X 0x30U NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_union, sizeof(union nv_pmu_pmgr_pwr_policy_union)); NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_relationship_union, sizeof(union nv_pmu_pmgr_pwr_policy_relationship_union)); -#define NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS 2 +#define NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS 2U struct nv_pmu_perf_domain_group_limits { u32 values[NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS]; } ; -#define NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT 0x6 +#define NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT 0x6U struct nv_pmu_pmgr_pwr_policy_desc_header { struct nv_pmu_boardobjgrp_e32 super; @@ -338,15 +338,15 @@ struct nv_pmu_pmgr_pwr_policy_pack { struct nv_pmu_pmgr_pwr_violation_desc violations; }; -#define NV_PMU_PMGR_CMD_ID_SET_OBJECT (0x00000000) +#define NV_PMU_PMGR_CMD_ID_SET_OBJECT (0x00000000U) -#define NV_PMU_PMGR_MSG_ID_QUERY (0x00000002) +#define NV_PMU_PMGR_MSG_ID_QUERY (0x00000002U) -#define NV_PMU_PMGR_CMD_ID_PWR_DEVICES_QUERY (0x00000001) +#define NV_PMU_PMGR_CMD_ID_PWR_DEVICES_QUERY (0x00000001U) -#define NV_PMU_PMGR_CMD_ID_LOAD (0x00000006) +#define NV_PMU_PMGR_CMD_ID_LOAD (0x00000006U) -#define NV_PMU_PMGR_CMD_ID_UNLOAD (0x00000007) +#define NV_PMU_PMGR_CMD_ID_UNLOAD (0x00000007U) struct nv_pmu_pmgr_cmd_set_object { u8 cmd_type; @@ -355,15 +355,15 @@ struct nv_pmu_pmgr_cmd_set_object { struct nv_pmu_allocation object; }; -#define NV_PMU_PMGR_SET_OBJECT_ALLOC_OFFSET (0x04) +#define NV_PMU_PMGR_SET_OBJECT_ALLOC_OFFSET (0x04U) -#define NV_PMU_PMGR_OBJECT_I2C_DEVICE_DESC_TABLE (0x00000000) +#define NV_PMU_PMGR_OBJECT_I2C_DEVICE_DESC_TABLE (0x00000000U) -#define NV_PMU_PMGR_OBJECT_PWR_DEVICE_DESC_TABLE (0x00000001) +#define NV_PMU_PMGR_OBJECT_PWR_DEVICE_DESC_TABLE (0x00000001U) -#define NV_PMU_PMGR_OBJECT_PWR_MONITOR (0x00000002) +#define NV_PMU_PMGR_OBJECT_PWR_MONITOR (0x00000002U) -#define NV_PMU_PMGR_OBJECT_PWR_POLICY (0x00000005) +#define NV_PMU_PMGR_OBJECT_PWR_POLICY (0x00000005U) struct nv_pmu_pmgr_pwr_devices_query_payload { struct { @@ -380,7 +380,7 @@ struct nv_pmu_pmgr_cmd_pwr_devices_query { struct nv_pmu_allocation payload; }; -#define NV_PMU_PMGR_PWR_DEVICES_QUERY_ALLOC_OFFSET (0x08) +#define NV_PMU_PMGR_PWR_DEVICES_QUERY_ALLOC_OFFSET (0x08U) struct nv_pmu_pmgr_cmd_load { u8 cmd_type; @@ -400,11 +400,11 @@ struct nv_pmu_pmgr_cmd { }; }; -#define NV_PMU_PMGR_MSG_ID_SET_OBJECT (0x00000000) +#define NV_PMU_PMGR_MSG_ID_SET_OBJECT (0x00000000U) -#define NV_PMU_PMGR_MSG_ID_LOAD (0x00000004) +#define NV_PMU_PMGR_MSG_ID_LOAD (0x00000004U) -#define NV_PMU_PMGR_MSG_ID_UNLOAD (0x00000005) +#define NV_PMU_PMGR_MSG_ID_UNLOAD (0x00000005U) struct nv_pmu_pmgr_msg_set_object { u8 msg_type; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h index f2edd6c69..0161719ad 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h @@ -26,13 +26,13 @@ #include #include "ctrl/ctrlvolt.h" -#define NV_PMU_VOLT_VALUE_0V_IN_UV (0) +#define NV_PMU_VOLT_VALUE_0V_IN_UV (0U) /* ------------- VOLT_RAIL's GRP_SET defines and structures ------------- */ -#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL 0x00 -#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE 0x01 -#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY 0x02 +#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL 0x00U +#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE 0x01U +#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY 0x02U struct nv_pmu_volt_volt_rail_boardobjgrp_set_header { @@ -264,17 +264,17 @@ struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin { rail_list; }; -#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) -#define NV_PMU_VOLT_CMD_ID_RPC (0x00000001) -#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) -#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN (0x00000004) +#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET (0x00000000U) +#define NV_PMU_VOLT_CMD_ID_RPC (0x00000001U) +#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002U) +#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN (0x00000004U) /*! * PMU VOLT RPC calls. */ -#define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000) -#define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE (0x00000002) -#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE (0x00000003) +#define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000U) +#define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE (0x00000002U) +#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE (0x00000003U) struct nv_pmu_volt_cmd_rpc { u8 cmd_type; @@ -310,9 +310,9 @@ struct nv_pmu_volt_rpc { /*! * VOLT MSG ID definitions */ -#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_SET (0x00000000) -#define NV_PMU_VOLT_MSG_ID_RPC (0x00000001) -#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) +#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_SET (0x00000000U) +#define NV_PMU_VOLT_MSG_ID_RPC (0x00000001U) +#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002U) /*! * Message carrying the result of the VOLT RPC execution. @@ -335,7 +335,7 @@ struct nv_pmu_volt_msg { }; }; -#define NV_PMU_VF_INJECT_MAX_VOLT_RAILS (2) +#define NV_PMU_VF_INJECT_MAX_VOLT_RAILS (2U) struct nv_pmu_volt_volt_rail_list { u8 num_rails; @@ -350,13 +350,13 @@ struct nv_pmu_volt_volt_rail_list_v1 { }; /* VOLT RPC */ -#define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00 -#define NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE 0x01 -#define NV_PMU_RPC_ID_VOLT_LOAD 0x02 -#define NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE 0x03 -#define NV_PMU_RPC_ID_VOLT_VOLT_POLICY_SANITY_CHECK 0x04 -#define NV_PMU_RPC_ID_VOLT_TEST_EXECUTE 0x05 -#define NV_PMU_RPC_ID_VOLT__COUNT 0x06 +#define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00U +#define NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE 0x01U +#define NV_PMU_RPC_ID_VOLT_LOAD 0x02U +#define NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE 0x03U +#define NV_PMU_RPC_ID_VOLT_VOLT_POLICY_SANITY_CHECK 0x04U +#define NV_PMU_RPC_ID_VOLT_TEST_EXECUTE 0x05U +#define NV_PMU_RPC_ID_VOLT__COUNT 0x06U /* * Defines the structure that holds data