gpu: nvgpu: Wrappers for checking platform type

Add nvgpu_* wrappers for determining if we're running in simulation
or silicon, and if we're running in hypervisor.

The new wrappers require struct gk20a pointer, and gk20a_fence_wait()
did not have access to one. Add struct gk20a pointer as the first
parameter.

JIRA NVGPU-16

Change-Id: I73b2b8f091ca29fb1827054abd2adaf583710331
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1331565
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile.nvgpu

@@ -33,6 +33,7 @@ nvgpu-y := \
 	common/linux/log.o \
 	common/linux/nvgpu_mem.o \
 	common/linux/dma.o \
+	common/linux/soc.o \
 	common/mm/nvgpu_allocator.o \
 	common/mm/bitmap_allocator.o \
 	common/mm/buddy_allocator.o \

drivers/gpu/nvgpu/common/linux/soc.c

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <soc/tegra/chip-id.h>
+
+#include <nvgpu/soc.h>
+
+bool nvgpu_platform_is_silicon(struct gk20a *g)
+{
+	return tegra_platform_is_silicon();
+}
+
+bool nvgpu_platform_is_simulation(struct gk20a *g)
+{
+	return tegra_platform_is_linsim() || tegra_platform_is_vdk();
+}
+
+bool nvgpu_is_hypervisor_mode(struct gk20a *g)
+{
+	return is_tegra_hypervisor_mode();
+}

drivers/gpu/nvgpu/common/linux/timers.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -18,6 +18,7 @@
 #include <linux/delay.h>
 
 #include <nvgpu/timers.h>
+#include <nvgpu/soc.h>
 
 #include "gk20a/gk20a.h"
 
@@ -31,7 +32,7 @@ static int nvgpu_timeout_is_pre_silicon(struct nvgpu_timeout *timeout)
 	if (timeout->flags & NVGPU_TIMER_NO_PRE_SI)
 		return 0;
 
-	return !tegra_platform_is_silicon();
+	return !nvgpu_platform_is_silicon(timeout->g);
 }
 
 /**

drivers/gpu/nvgpu/common/nvgpu_common.c

@@ -19,6 +19,7 @@
 
 #include <nvgpu/kmem.h>
 #include <nvgpu/nvgpu_common.h>
+#include <nvgpu/soc.h>
 
 #include "gk20a/gk20a_scale.h"
 #include "gk20a/gk20a.h"
@@ -60,7 +61,7 @@ static void nvgpu_init_vars(struct gk20a *g)
 static void nvgpu_init_timeout(struct gk20a *g)
 {
 	g->gr_idle_timeout_default = CONFIG_GK20A_DEFAULT_TIMEOUT;
-	if (tegra_platform_is_silicon())
+	if (nvgpu_platform_is_silicon(g))
 		g->timeouts_enabled = true;
 }
 
@@ -85,17 +86,17 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
 	 * power features and for silicon platforms, read from platform data
 	 */
 	g->slcg_enabled =
-		tegra_platform_is_silicon() ? platform->enable_slcg : false;
+		nvgpu_platform_is_silicon(g) ? platform->enable_slcg : false;
 	g->blcg_enabled =
-		tegra_platform_is_silicon() ? platform->enable_blcg : false;
+		nvgpu_platform_is_silicon(g) ? platform->enable_blcg : false;
 	g->elcg_enabled =
-		tegra_platform_is_silicon() ? platform->enable_elcg : false;
+		nvgpu_platform_is_silicon(g) ? platform->enable_elcg : false;
 	g->elpg_enabled =
-		tegra_platform_is_silicon() ? platform->enable_elpg : false;
+		nvgpu_platform_is_silicon(g) ? platform->enable_elpg : false;
 	g->aelpg_enabled =
-		tegra_platform_is_silicon() ? platform->enable_aelpg : false;
+		nvgpu_platform_is_silicon(g) ? platform->enable_aelpg : false;
 	g->mscg_enabled =
-		tegra_platform_is_silicon() ? platform->enable_mscg : false;
+		nvgpu_platform_is_silicon(g) ? platform->enable_mscg : false;
 
 	/* set default values to aelpg parameters */
 	g->pmu.aelpg_param[0] = APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US;

drivers/gpu/nvgpu/gk20a/bus_gk20a.c

@@ -14,10 +14,9 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <soc/tegra/chip-id.h>
-
 #include <nvgpu/page_allocator.h>
 #include <nvgpu/log.h>
+#include <nvgpu/soc.h>
 
 #include "gk20a.h"
 
@@ -31,7 +30,7 @@ void gk20a_bus_init_hw(struct gk20a *g)
 	struct gk20a_platform *platform = gk20a_get_platform(g->dev);
 
 	/* enable pri timeout only on silicon */
-	if (tegra_platform_is_silicon()) {
+	if (nvgpu_platform_is_silicon(g)) {
 		gk20a_writel(g,
 			timer_pri_timeout_r(),
 			timer_pri_timeout_period_f(
@@ -46,7 +45,7 @@ void gk20a_bus_init_hw(struct gk20a *g)
 			timer_pri_timeout_en_en_disabled_f());
 	}
 
-	if (!tegra_platform_is_silicon())
+	if (!nvgpu_platform_is_silicon(g))
 		gk20a_writel(g, bus_intr_en_0_r(), 0x0);
 	else
 		gk20a_writel(g, bus_intr_en_0_r(),

drivers/gpu/nvgpu/gk20a/ce2_gk20a.c

@@ -618,7 +618,8 @@ int gk20a_ce_execute_ops(struct device *dev,
 		memcpy((void *)&ce_cmd_buf_fence_in,
 				(void *)(cmd_buf_cpu_va + fence_index),
 				sizeof(struct gk20a_fence *));
-		ret = gk20a_fence_wait(ce_cmd_buf_fence_in, gk20a_get_gr_idle_timeout(g));
+		ret = gk20a_fence_wait(g, ce_cmd_buf_fence_in,
+				       gk20a_get_gr_idle_timeout(g));
 
 		gk20a_fence_put(ce_cmd_buf_fence_in);
 		/* Reset the stored last pre-sync */
@@ -645,7 +646,8 @@ int gk20a_ce_execute_ops(struct device *dev,
 	if (methodSize) {
 		/* TODO: Remove CPU pre-fence wait */
 		if (gk20a_fence_in) {
-			ret = gk20a_fence_wait(gk20a_fence_in, gk20a_get_gr_idle_timeout(g));
+			ret = gk20a_fence_wait(g, gk20a_fence_in,
+					       gk20a_get_gr_idle_timeout(g));
 			gk20a_fence_put(gk20a_fence_in);
 			if (ret)
 				goto noop;

drivers/gpu/nvgpu/gk20a/clk_gk20a.c

@@ -25,6 +25,7 @@
 #include "gk20a.h"
 
 #include <nvgpu/log.h>
+#include <nvgpu/soc.h>
 
 #include <nvgpu/hw/gk20a/hw_trim_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
@@ -268,7 +269,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk,
 
 	gk20a_dbg_fn("");
 
-	if (!tegra_platform_is_silicon())
+	if (!nvgpu_platform_is_silicon(g))
 		return 0;
 
 	/* get old coefficients */

drivers/gpu/nvgpu/gk20a/fence_gk20a.c

@@ -19,6 +19,7 @@
 
 #include <nvgpu/semaphore.h>
 #include <nvgpu/kmem.h>
+#include <nvgpu/soc.h>
 
 #include "gk20a.h"
 #include "channel_gk20a.h"
@@ -80,10 +81,10 @@ static inline bool gk20a_fence_is_valid(struct gk20a_fence *f)
 	return valid;
 }
 
-int gk20a_fence_wait(struct gk20a_fence *f, int timeout)
+int gk20a_fence_wait(struct gk20a *g, struct gk20a_fence *f, int timeout)
 {
 	if (f && gk20a_fence_is_valid(f)) {
-		if (!tegra_platform_is_silicon())
+		if (!nvgpu_platform_is_silicon(g))
 			timeout = (u32)MAX_SCHEDULE_TIMEOUT;
 		return f->ops->wait(f, timeout);
 	}

drivers/gpu/nvgpu/gk20a/fence_gk20a.h

@@ -25,6 +25,7 @@ struct sync_timeline;
 struct sync_fence;
 struct nvgpu_semaphore;
 struct channel_gk20a;
+struct gk20a;
 
 struct gk20a_fence_ops;
 
@@ -83,7 +84,7 @@ void gk20a_init_fence(struct gk20a_fence *f,
 /* Fence operations */
 void gk20a_fence_put(struct gk20a_fence *f);
 struct gk20a_fence *gk20a_fence_get(struct gk20a_fence *f);
-int gk20a_fence_wait(struct gk20a_fence *f, int timeout);
+int gk20a_fence_wait(struct gk20a *g, struct gk20a_fence *f, int timeout);
 bool gk20a_fence_is_expired(struct gk20a_fence *f);
 int gk20a_fence_install_fd(struct gk20a_fence *f);
 

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -31,6 +31,7 @@
 #include <nvgpu/semaphore.h>
 #include <nvgpu/kmem.h>
 #include <nvgpu/log.h>
+#include <nvgpu/soc.h>
 
 #include "gk20a.h"
 #include "debug_gk20a.h"
@@ -3349,7 +3350,7 @@ static void gk20a_fifo_apply_pb_timeout(struct gk20a *g)
 {
 	u32 timeout;
 
-	if (tegra_platform_is_silicon()) {
+	if (nvgpu_platform_is_silicon(g)) {
 		timeout = gk20a_readl(g, fifo_pb_timeout_r());
 		timeout &= ~fifo_pb_timeout_detection_enabled_f();
 		gk20a_writel(g, fifo_pb_timeout_r(), timeout);

drivers/gpu/nvgpu/gk20a/gk20a.c

@@ -43,6 +43,7 @@
 #include <nvgpu/kmem.h>
 #include <nvgpu/allocator.h>
 #include <nvgpu/timers.h>
+#include <nvgpu/soc.h>
 
 #include "gk20a.h"
 #include "debug_gk20a.h"
@@ -295,7 +296,7 @@ static int gk20a_init_support(struct platform_device *dev)
 		goto fail;
 	}
 
-	if (tegra_cpu_is_asim()) {
+	if (nvgpu_platform_is_simulation(g)) {
 		err = gk20a_init_sim_support(dev);
 		if (err)
 			goto fail;
@@ -954,9 +955,6 @@ static int gk20a_probe(struct platform_device *dev)
 		return -ENODATA;
 	}
 
-	if (tegra_platform_is_linsim() || tegra_platform_is_vdk())
-		platform->is_fmodel = true;
-
 	gk20a_dbg_fn("");
 
 	platform_set_drvdata(dev, platform);
@@ -973,6 +971,9 @@ static int gk20a_probe(struct platform_device *dev)
 	set_gk20a(dev, gk20a);
 	gk20a->dev = &dev->dev;
 
+	if (nvgpu_platform_is_simulation(gk20a))
+		platform->is_fmodel = true;
+
 	nvgpu_kmem_init(gk20a);
 
 	gk20a->irq_stall = platform_get_irq(dev, 0);
@@ -1030,7 +1031,7 @@ static int gk20a_probe(struct platform_device *dev)
 		return err;
 	}
 
-	gk20a->mm.has_physical_mode = !is_tegra_hypervisor_mode();
+	gk20a->mm.has_physical_mode = !nvgpu_is_hypervisor_mode(gk20a);
 
 	return 0;
 }

drivers/gpu/nvgpu/gk20a/gk20a.h

@@ -34,7 +34,6 @@ struct dbg_profiler_object_data;
 #include <nvgpu/lock.h>
 #include <linux/nvgpu.h>
 #include <linux/irqreturn.h>
-#include <soc/tegra/chip-id.h>
 #include <linux/version.h>
 #include <linux/atomic.h>
 #include <linux/cdev.h>

drivers/gpu/nvgpu/gk20a/mm_gk20a.c

@@ -569,7 +569,7 @@ static int gk20a_vidmem_clear_all(struct gk20a *g)
 				   NVGPU_TIMER_CPU_TIMER);
 
 		do {
-			err = gk20a_fence_wait(gk20a_fence_out,
+			err = gk20a_fence_wait(g, gk20a_fence_out,
 					       gk20a_get_gr_idle_timeout(g));
 		} while (err == -ERESTARTSYS &&
 			 !nvgpu_timeout_expired(&timeout));
@@ -2560,7 +2560,7 @@ static int gk20a_gmmu_clear_vidmem_mem(struct gk20a *g, struct nvgpu_mem *mem)
 				   NVGPU_TIMER_CPU_TIMER);
 
 		do {
-			err = gk20a_fence_wait(gk20a_last_fence,
+			err = gk20a_fence_wait(g, gk20a_last_fence,
 					       gk20a_get_gr_idle_timeout(g));
 		} while (err == -ERESTARTSYS &&
 			 !nvgpu_timeout_expired(&timeout));

drivers/gpu/nvgpu/gk20a/pmu_gk20a.c

@@ -3642,19 +3642,10 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id)
 
 	gk20a_dbg_fn("");
 
-	if (tegra_cpu_is_asim()) {
+	gk20a_writel(g, pwr_pmu_pg_idlefilth_r(pg_engine_id),
-		/* TBD: calculate threshold for silicon */
+		PMU_PG_IDLE_THRESHOLD);
-		gk20a_writel(g, pwr_pmu_pg_idlefilth_r(pg_engine_id),
+	gk20a_writel(g, pwr_pmu_pg_ppuidlefilth_r(pg_engine_id),
-			PMU_PG_IDLE_THRESHOLD_SIM);
+		PMU_PG_POST_POWERUP_IDLE_THRESHOLD);
-		gk20a_writel(g, pwr_pmu_pg_ppuidlefilth_r(pg_engine_id),
-			PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM);
-	} else {
-		/* TBD: calculate threshold for silicon */
-		gk20a_writel(g, pwr_pmu_pg_idlefilth_r(pg_engine_id),
-			PMU_PG_IDLE_THRESHOLD);
-		gk20a_writel(g, pwr_pmu_pg_ppuidlefilth_r(pg_engine_id),
-			PMU_PG_POST_POWERUP_IDLE_THRESHOLD);
-	}
 
 	if (g->ops.pmu.pmu_pg_init_param)
 		g->ops.pmu.pmu_pg_init_param(g, pg_engine_id);

drivers/gpu/nvgpu/gm20b/clk_gm20b.c

@@ -31,6 +31,8 @@
 #include "gk20a/gk20a.h"
 #include "clk_gm20b.h"
 
+#include <nvgpu/soc.h>
+
 #include <nvgpu/hw/gm20b/hw_trim_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_timer_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_therm_gm20b.h>
@@ -835,7 +837,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct pll *gpll_new,
 
 	gk20a_dbg_fn("");
 
-	if (!tegra_platform_is_silicon())
+	if (!nvgpu_platform_is_silicon(g))
 		return 0;
 
 	/* get old coefficients */

drivers/gpu/nvgpu/gp106/pmu_gp106.c

@@ -71,7 +71,7 @@ static int gp106_pmu_enable_hw(struct pmu_gk20a *pmu, bool enable)
 				return 0;
 			}
 			udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT);
-		} while (--retries || !tegra_platform_is_silicon());
+		} while (--retries);
 
 		/* If scrubbing timeout, keep PMU in reset state */
 		gk20a_writel(g, pwr_falcon_engine_r(),

drivers/gpu/nvgpu/gp106/therm_gp106.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -87,12 +87,6 @@ static int gp106_elcg_init_idle_filters(struct gk20a *g)
 		active_engine_id = f->active_engines_list[engine_id];
 		gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
 
-		if (tegra_platform_is_linsim()) {
-			gate_ctrl = set_field(gate_ctrl,
-				therm_gate_ctrl_eng_delay_after_m(),
-				therm_gate_ctrl_eng_delay_after_f(4));
-		}
-
 		gate_ctrl = set_field(gate_ctrl,
 			therm_gate_ctrl_eng_idle_filt_exp_m(),
 			therm_gate_ctrl_eng_idle_filt_exp_f(2));

drivers/gpu/nvgpu/gp10b/therm_gp10b.c

@@ -1,9 +1,7 @@
 /*
- * drivers/gpu/nvgpu/gm20b/therm_gk20a.c
- *
  * GP10B Therm
  *
- * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -17,6 +15,8 @@
 
 #include "gk20a/gk20a.h"
 
+#include <nvgpu/soc.h>
+
 #include <nvgpu/hw/gp10b/hw_therm_gp10b.h>
 
 static int gp10b_init_therm_setup_hw(struct gk20a *g)
@@ -92,7 +92,7 @@ static int gp10b_elcg_init_idle_filters(struct gk20a *g)
 		active_engine_id = f->active_engines_list[engine_id];
 		gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
 
-		if (tegra_platform_is_linsim()) {
+		if (nvgpu_platform_is_simulation(g)) {
 			gate_ctrl = set_field(gate_ctrl,
 				therm_gate_ctrl_eng_delay_after_m(),
 				therm_gate_ctrl_eng_delay_after_f(4));

drivers/gpu/nvgpu/include/nvgpu/soc.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#ifndef __NVGPU_SOC_H__
+#define __NVGPU_SOC_H__
+
+struct gk20a;
+
+bool nvgpu_platform_is_silicon(struct gk20a *g);
+bool nvgpu_platform_is_simulation(struct gk20a *g);
+bool nvgpu_is_hypervisor_mode(struct gk20a *g);
+
+#endif

drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c

@@ -46,6 +46,7 @@
 #endif
 
 #include <linux/platform/tegra/tegra_emc.h>
+#include <soc/tegra/chip-id.h>
 
 #include <nvgpu/kmem.h>