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gpu: nvpgu: move zbc structs to priv header

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Move nvgpu_gr_zbc_entry and nvgpu_gr_zbc to a priv header and
add APIs to access members of those structs.

JIRA NVGPU-3060

Change-Id: I1255f3ebda03f599aed3706136c0909491023067
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2091214
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Nitin Kumbhar
2019-04-06 13:00:28 +05:30
committed by mobile promotions
parent ff69c5c210
commit 1a843ba051
8 changed files with 149 additions and 45 deletions
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66
drivers/gpu/nvgpu/common/gr/zbc.c
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@@ -596,3 +596,69 @@ void nvgpu_gr_zbc_deinit(struct gk20a *g, struct nvgpu_gr_zbc *zbc)
nvgpu_kfree(g, zbc->zbc_s_tbl);
nvgpu_kfree(g, zbc);
}
struct nvgpu_gr_zbc_entry *nvgpu_gr_zbc_entry_alloc(struct gk20a *g)
{
return nvgpu_kzalloc(g, sizeof(struct nvgpu_gr_zbc_entry));
}
void nvgpu_gr_zbc_entry_free(struct gk20a *g, struct nvgpu_gr_zbc_entry *entry)
{
nvgpu_kfree(g, entry);
}
u32 nvgpu_gr_zbc_get_entry_color_ds(struct nvgpu_gr_zbc_entry *entry,
int idx)
{
return entry->color_ds[idx];
}
void nvgpu_gr_zbc_set_entry_color_ds(struct nvgpu_gr_zbc_entry *entry,
int idx, u32 ds)
{
entry->color_ds[idx] = ds;
}
u32 nvgpu_gr_zbc_get_entry_color_l2(struct nvgpu_gr_zbc_entry *entry,
int idx)
{
return entry->color_l2[idx];
}
void nvgpu_gr_zbc_set_entry_color_l2(struct nvgpu_gr_zbc_entry *entry,
int idx, u32 l2)
{
entry->color_l2[idx] = l2;
}
u32 nvgpu_gr_zbc_get_entry_depth(struct nvgpu_gr_zbc_entry *entry)
{
return entry->depth;
}
void nvgpu_gr_zbc_set_entry_depth(struct nvgpu_gr_zbc_entry *entry,
u32 depth)
{
entry->depth = depth;
}
u32 nvgpu_gr_zbc_get_entry_type(struct nvgpu_gr_zbc_entry *entry)
{
return entry->type;
}
void nvgpu_gr_zbc_set_entry_type(struct nvgpu_gr_zbc_entry *entry,
u32 type)
{
entry->type = type;
}
u32 nvgpu_gr_zbc_get_entry_format(struct nvgpu_gr_zbc_entry *entry)
{
return entry->format;
}
void nvgpu_gr_zbc_set_entry_format(struct nvgpu_gr_zbc_entry *entry,
u32 format)
{
entry->format = format;
}

21
drivers/gpu/nvgpu/common/gr/zbc_priv.h
View File

@@ -56,5 +56,26 @@ struct zbc_s_table {
u32 ref_cnt;
};
struct nvgpu_gr_zbc_entry {
u32 color_ds[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
u32 color_l2[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
u32 depth;
u32 type; /* color or depth */
u32 format;
};
struct nvgpu_gr_zbc {
struct nvgpu_mutex zbc_lock;
struct zbc_color_table *zbc_col_tbl;
struct zbc_depth_table *zbc_dep_tbl;
struct zbc_s_table *zbc_s_tbl;
s32 max_default_color_index;
s32 max_default_depth_index;
s32 max_default_s_index;
u32 max_used_color_index;
u32 max_used_depth_index;
u32 max_used_s_index;
};
#endif /* GR_ZBC_H */

1
drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c
View File

@@ -53,6 +53,7 @@
#include "common/vgpu/ivc/comm_vgpu.h"
#include "common/gr/zcull_priv.h"
#include "common/gr/zbc_priv.h"
static int vgpu_gr_set_ctxsw_preemption_mode(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx,

21
drivers/gpu/nvgpu/hal/gr/zbc/zbc_gm20b.c
View File

@@ -33,16 +33,21 @@ int gm20b_gr_zbc_add_color(struct gk20a *g,
{
/* update ds table */
nvgpu_writel(g, gr_ds_zbc_color_r_r(),
gr_ds_zbc_color_r_val_f(color_val->color_ds[0]));
gr_ds_zbc_color_r_val_f(
nvgpu_gr_zbc_get_entry_color_ds(color_val, 0)));
nvgpu_writel(g, gr_ds_zbc_color_g_r(),
gr_ds_zbc_color_g_val_f(color_val->color_ds[1]));
gr_ds_zbc_color_g_val_f(
nvgpu_gr_zbc_get_entry_color_ds(color_val, 1)));
nvgpu_writel(g, gr_ds_zbc_color_b_r(),
gr_ds_zbc_color_b_val_f(color_val->color_ds[2]));
gr_ds_zbc_color_b_val_f(
nvgpu_gr_zbc_get_entry_color_ds(color_val, 2)));
nvgpu_writel(g, gr_ds_zbc_color_a_r(),
gr_ds_zbc_color_a_val_f(color_val->color_ds[3]));
gr_ds_zbc_color_a_val_f(
nvgpu_gr_zbc_get_entry_color_ds(color_val, 3)));
nvgpu_writel(g, gr_ds_zbc_color_fmt_r(),
gr_ds_zbc_color_fmt_val_f(color_val->format));
gr_ds_zbc_color_fmt_val_f(
nvgpu_gr_zbc_get_entry_format(color_val)));
nvgpu_writel(g, gr_ds_zbc_tbl_index_r(),
gr_ds_zbc_tbl_index_val_f(index + NVGPU_GR_ZBC_STARTOF_TABLE));
@@ -61,10 +66,12 @@ int gm20b_gr_zbc_add_depth(struct gk20a *g,
{
/* update ds table */
nvgpu_writel(g, gr_ds_zbc_z_r(),
gr_ds_zbc_z_val_f(depth_val->depth));
gr_ds_zbc_z_val_f(
nvgpu_gr_zbc_get_entry_depth(depth_val)));
nvgpu_writel(g, gr_ds_zbc_z_fmt_r(),
gr_ds_zbc_z_fmt_val_f(depth_val->format));
gr_ds_zbc_z_fmt_val_f(
nvgpu_gr_zbc_get_entry_format(depth_val)));
nvgpu_writel(g, gr_ds_zbc_tbl_index_r(),
gr_ds_zbc_tbl_index_val_f(index + NVGPU_GR_ZBC_STARTOF_TABLE));

16
drivers/gpu/nvgpu/hal/gr/zbc/zbc_gp10b.c
View File

@@ -46,16 +46,17 @@ int gp10b_gr_zbc_add_color(struct gk20a *g,
g->ops.gr.zbc.get_gpcs_swdx_dss_zbc_c_format_reg(g);
nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_r_r(index),
color_val->color_ds[0]);
nvgpu_gr_zbc_get_entry_color_ds(color_val, 0));
nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_g_r(index),
color_val->color_ds[1]);
nvgpu_gr_zbc_get_entry_color_ds(color_val, 1));
nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_b_r(index),
color_val->color_ds[2]);
nvgpu_gr_zbc_get_entry_color_ds(color_val, 2));
nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_a_r(index),
color_val->color_ds[3]);
nvgpu_gr_zbc_get_entry_color_ds(color_val, 3));
zbc_c = nvgpu_readl(g, zbc_c_format_reg + (index & ~3U));
zbc_c &= ~(0x7fU << ((index % 4U) * 7U));
zbc_c |= color_val->format << ((index % 4U) * 7U);
zbc_c |= nvgpu_gr_zbc_get_entry_format(color_val) <<
((index % 4U) * 7U);
nvgpu_writel_loop(g, zbc_c_format_reg + (index & ~3U), zbc_c);
return 0;
@@ -68,10 +69,11 @@ int gp10b_gr_zbc_add_depth(struct gk20a *g,
u32 zbc_z_format_reg =
g->ops.gr.zbc.get_gpcs_swdx_dss_zbc_z_format_reg(g);
nvgpu_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth);
nvgpu_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index),
nvgpu_gr_zbc_get_entry_depth(depth_val));
zbc_z = nvgpu_readl(g, zbc_z_format_reg + (index & ~3U));
zbc_z &= ~(U32(0x7f) << (index % 4U) * 7U);
zbc_z |= depth_val->format << (index % 4U) * 7U;
zbc_z |= nvgpu_gr_zbc_get_entry_format(depth_val) << (index % 4U) * 7U;
nvgpu_writel(g, zbc_z_format_reg + (index & ~3U), zbc_z);
return 0;

6
drivers/gpu/nvgpu/hal/gr/zbc/zbc_gv11b.c
View File

@@ -43,11 +43,13 @@ int gv11b_gr_zbc_add_stencil(struct gk20a *g,
{
u32 zbc_s;
nvgpu_writel(g, gr_gpcs_swdx_dss_zbc_s_r(index), stencil_val->depth);
nvgpu_writel(g, gr_gpcs_swdx_dss_zbc_s_r(index),
nvgpu_gr_zbc_get_entry_depth(stencil_val));
zbc_s = nvgpu_readl(g, gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() +
(index & ~3U));
zbc_s &= ~(U32(0x7f) << (index % 4U) * 7U);
zbc_s |= stencil_val->format << (index % 4U) * 7U;
zbc_s |= nvgpu_gr_zbc_get_entry_format(stencil_val) <<
(index % 4U) * 7U;
nvgpu_writel(g, gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() +
(index & ~3U), zbc_s);

44
drivers/gpu/nvgpu/include/nvgpu/gr/zbc.h
View File

@@ -43,14 +43,8 @@ struct gk20a;
struct zbc_color_table;
struct zbc_depth_table;
struct zbc_s_table;
struct nvgpu_gr_zbc_entry {
u32 color_ds[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
u32 color_l2[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
u32 depth;
u32 type; /* color or depth */
u32 format;
};
struct nvgpu_gr_zbc_entry;
struct nvgpu_gr_zbc;
struct nvgpu_gr_zbc_query_params {
u32 color_ds[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
@@ -62,19 +56,6 @@ struct nvgpu_gr_zbc_query_params {
u32 index_size; /* [out] size, [in] index */
};
struct nvgpu_gr_zbc {
struct nvgpu_mutex zbc_lock;
struct zbc_color_table *zbc_col_tbl;
struct zbc_depth_table *zbc_dep_tbl;
struct zbc_s_table *zbc_s_tbl;
s32 max_default_color_index;
s32 max_default_depth_index;
s32 max_default_s_index;
u32 max_used_color_index;
u32 max_used_depth_index;
u32 max_used_s_index;
};
int nvgpu_gr_zbc_init(struct gk20a *g, struct nvgpu_gr_zbc **zbc);
void nvgpu_gr_zbc_deinit(struct gk20a *g, struct nvgpu_gr_zbc *zbc);
int nvgpu_gr_zbc_load_table(struct gk20a *g, struct nvgpu_gr_zbc *zbc);
@@ -94,4 +75,25 @@ bool nvgpu_gr_zbc_add_type_stencil(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
int nvgpu_gr_zbc_load_stencil_default_tbl(struct gk20a *g,
struct nvgpu_gr_zbc *zbc);
int nvgpu_gr_zbc_load_stencil_tbl(struct gk20a *g, struct nvgpu_gr_zbc *zbc);
struct nvgpu_gr_zbc_entry *nvgpu_gr_zbc_entry_alloc(struct gk20a *g);
void nvgpu_gr_zbc_entry_free(struct gk20a *g, struct nvgpu_gr_zbc_entry *entry);
u32 nvgpu_gr_zbc_get_entry_color_ds(struct nvgpu_gr_zbc_entry *entry,
int idx);
void nvgpu_gr_zbc_set_entry_color_ds(struct nvgpu_gr_zbc_entry *entry,
int idx, u32 ds);
u32 nvgpu_gr_zbc_get_entry_color_l2(struct nvgpu_gr_zbc_entry *entry,
int idx);
void nvgpu_gr_zbc_set_entry_color_l2(struct nvgpu_gr_zbc_entry *entry,
int idx, u32 l2);
u32 nvgpu_gr_zbc_get_entry_depth(struct nvgpu_gr_zbc_entry *entry);
void nvgpu_gr_zbc_set_entry_depth(struct nvgpu_gr_zbc_entry *entry,
u32 depth);
u32 nvgpu_gr_zbc_get_entry_type(struct nvgpu_gr_zbc_entry *entry);
void nvgpu_gr_zbc_set_entry_type(struct nvgpu_gr_zbc_entry *entry,
u32 type);
u32 nvgpu_gr_zbc_get_entry_format(struct nvgpu_gr_zbc_entry *entry);
void nvgpu_gr_zbc_set_entry_format(struct nvgpu_gr_zbc_entry *entry,
u32 format);
#endif /* NVGPU_GR_ZBC_H */

19
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
View File

@@ -1706,24 +1706,27 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
case NVGPU_GPU_IOCTL_ZBC_SET_TABLE:
set_table_args = (struct nvgpu_gpu_zbc_set_table_args *)buf;
zbc_val = nvgpu_kzalloc(g, sizeof(struct nvgpu_gr_zbc_entry));
zbc_val = nvgpu_gr_zbc_entry_alloc(g);
if (zbc_val == NULL)
return -ENOMEM;
zbc_val->format = set_table_args->format;
zbc_val->type = set_table_args->type;
nvgpu_gr_zbc_set_entry_format(zbc_val, set_table_args->format);
nvgpu_gr_zbc_set_entry_type(zbc_val, set_table_args->type);
nvgpu_speculation_barrier();
switch (zbc_val->type) {
switch (nvgpu_gr_zbc_get_entry_type(zbc_val)) {
case NVGPU_GR_ZBC_TYPE_COLOR:
for (i = 0U; i < NVGPU_GR_ZBC_COLOR_VALUE_SIZE; i++) {
zbc_val->color_ds[i] = set_table_args->color_ds[i];
zbc_val->color_l2[i] = set_table_args->color_l2[i];
nvgpu_gr_zbc_set_entry_color_ds(zbc_val, i,
set_table_args->color_ds[i]);
nvgpu_gr_zbc_set_entry_color_l2(zbc_val, i,
set_table_args->color_l2[i]);
}
break;
case NVGPU_GR_ZBC_TYPE_DEPTH:
case NVGPU_GR_ZBC_TYPE_STENCIL:
zbc_val->depth = set_table_args->depth;
nvgpu_gr_zbc_set_entry_depth(zbc_val,
set_table_args->depth);
break;
default:
err = -EINVAL;
@@ -1739,7 +1742,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
}
if (zbc_val)
nvgpu_kfree(g, zbc_val);
nvgpu_gr_zbc_entry_free(g, zbc_val);
break;
case NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE:
query_table_args = (struct nvgpu_gpu_zbc_query_table_args *)buf;