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gpu: nvgpu: reduce code complexity in common.gr

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Reduce the code complexity in gr_init_setup_hw function from
13 to 8.
Remove all NULL checking for those hals which are initialized to
valid a function for all supporting chips.

Jira NVGPU-3661

Change-Id: I564dd87d72fcc66c31c9aaa62ef7bec505fd9510
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2145470
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-06-28 15:01:16 -07:00
committed by mobile promotions
parent cd4fa084c1
commit 1aaff7a48c
1 changed files with 4 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/gpu/nvgpu/common/gr/gr.c
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@@ -178,7 +178,6 @@ int nvgpu_gr_suspend(struct gk20a *g)
return ret; return ret;
} }
static int gr_init_setup_hw(struct gk20a *g) static int gr_init_setup_hw(struct gk20a *g)
{ {
struct nvgpu_gr *gr = g->gr; struct nvgpu_gr *gr = g->gr;
@@ -186,9 +185,7 @@ static int gr_init_setup_hw(struct gk20a *g)
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
if (g->ops.gr.init.gpc_mmu != NULL) { g->ops.gr.init.gpc_mmu(g);
g->ops.gr.init.gpc_mmu(g);
}
/* load gr floorsweeping registers */ /* load gr floorsweeping registers */
g->ops.gr.init.pes_vsc_stream(g); g->ops.gr.init.pes_vsc_stream(g);
@@ -219,9 +216,7 @@ static int gr_init_setup_hw(struct gk20a *g)
g->ops.gr.intr.set_hww_esr_report_mask(g); g->ops.gr.intr.set_hww_esr_report_mask(g);
/* enable TPC exceptions per GPC */ /* enable TPC exceptions per GPC */
if (g->ops.gr.intr.enable_gpc_exceptions != NULL) { g->ops.gr.intr.enable_gpc_exceptions(g, gr->config);
g->ops.gr.intr.enable_gpc_exceptions(g, gr->config);
}
/* enable ECC for L1/SM */ /* enable ECC for L1/SM */
if (g->ops.gr.init.ecc_scrub_reg != NULL) { if (g->ops.gr.init.ecc_scrub_reg != NULL) {
@@ -243,13 +238,8 @@ static int gr_init_setup_hw(struct gk20a *g)
/* /*
* Disable both surface and LG coalesce. * Disable both surface and LG coalesce.
*/ */
if (g->ops.gr.init.su_coalesce != NULL) { g->ops.gr.init.su_coalesce(g, 0);
g->ops.gr.init.su_coalesce(g, 0); g->ops.gr.init.lg_coalesce(g, 0);
}
if (g->ops.gr.init.lg_coalesce != NULL) {
g->ops.gr.init.lg_coalesce(g, 0);
}
if (g->ops.gr.init.preemption_state != NULL) { if (g->ops.gr.init.preemption_state != NULL) {
err = g->ops.gr.init.preemption_state(g); err = g->ops.gr.init.preemption_state(g);