From 1ab3f73230993dff527bd9a20dc56ea2590d65a3 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Wed, 27 Nov 2019 17:55:23 -0500 Subject: [PATCH] gpu: nvgpu: unit: improve coverage for gm20b channel HAL Add unit test for the following HAL: - gm20b_channel_force_ctx_reload Jira NVGPU-4384 Change-Id: Icb802348349a790371e6d84efe449c309105c5e8 Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2250014 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/hal/fifo/channel_gm20b_fusa.c | 4 +-- drivers/gpu/nvgpu/libnvgpu-drv_safe.export | 1 + .../fifo/channel/gm20b/nvgpu-channel-gm20b.c | 26 ++++++++++++++++ .../fifo/channel/gm20b/nvgpu-channel-gm20b.h | 31 +++++++++++++++++-- 4 files changed, 58 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/fifo/channel_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/channel_gm20b_fusa.c index e6cc80019..568bd60d6 100644 --- a/drivers/gpu/nvgpu/hal/fifo/channel_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/channel_gm20b_fusa.c @@ -61,8 +61,8 @@ void gm20b_channel_bind(struct nvgpu_channel *c) void gm20b_channel_force_ctx_reload(struct nvgpu_channel *ch) { struct gk20a *g = ch->g; - u32 reg = gk20a_readl(g, ccsr_channel_r(ch->chid)); + u32 reg = nvgpu_readl(g, ccsr_channel_r(ch->chid)); - gk20a_writel(g, ccsr_channel_r(ch->chid), + nvgpu_writel(g, ccsr_channel_r(ch->chid), reg | ccsr_channel_force_ctx_reload_true_f()); } diff --git a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export index 313cce600..657dee72a 100644 --- a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export +++ b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export @@ -26,6 +26,7 @@ gk20a_runlist_wait_pending gk20a_runlist_write_state gk20a_vm_release_share gm20b_channel_bind +gm20b_channel_force_ctx_reload gm20b_fb_tlb_invalidate gm20b_mm_get_big_page_sizes gm20b_gr_falcon_get_fecs_ctx_state_store_major_rev_id diff --git a/userspace/units/fifo/channel/gm20b/nvgpu-channel-gm20b.c b/userspace/units/fifo/channel/gm20b/nvgpu-channel-gm20b.c index b17204604..16033f983 100644 --- a/userspace/units/fifo/channel/gm20b/nvgpu-channel-gm20b.c +++ b/userspace/units/fifo/channel/gm20b/nvgpu-channel-gm20b.c @@ -89,10 +89,36 @@ done: return ret; } +int test_gm20b_channel_force_ctx_reload(struct unit_module *m, + struct gk20a *g, void *args) +{ + bool privileged = false; + u32 runlist_id = NVGPU_INVALID_RUNLIST_ID; + struct nvgpu_channel *ch; + int ret = UNIT_FAIL; + + ch = nvgpu_channel_open_new(g, runlist_id, + privileged, getpid(), getpid()); + assert(ch); + + nvgpu_writel(g, ccsr_channel_r(ch->chid), 0); + gm20b_channel_force_ctx_reload(ch); + assert((nvgpu_readl(g, ccsr_channel_r(ch->chid)) & + ccsr_channel_force_ctx_reload_true_f()) != 0); + + ret = UNIT_SUCCESS; +done: + if (ch) { + nvgpu_channel_close(ch); + } + + return ret; +} struct unit_module_test nvgpu_channel_gm20b_tests[] = { UNIT_TEST(init_support, test_fifo_init_support, NULL, 0), UNIT_TEST(bind, test_gm20b_channel_bind, NULL, 0), + UNIT_TEST(force_ctx_reload, test_gm20b_channel_force_ctx_reload, NULL, 0), UNIT_TEST(remove_support, test_fifo_remove_support, NULL, 0), }; diff --git a/userspace/units/fifo/channel/gm20b/nvgpu-channel-gm20b.h b/userspace/units/fifo/channel/gm20b/nvgpu-channel-gm20b.h index 5f3ddbfcb..16793eb5c 100644 --- a/userspace/units/fifo/channel/gm20b/nvgpu-channel-gm20b.h +++ b/userspace/units/fifo/channel/gm20b/nvgpu-channel-gm20b.h @@ -36,16 +36,18 @@ struct gk20a; /** * Test specification for: test_gm20b_channel_bind * - * Description: Branch coverage for gm20b_channel_bind + * Description: Bind channel to HW * * Test Type: Feature based * + * Targets: gm20b_channel_bind + * * Input: test_fifo_init_support() run for this GPU * * Steps: * - Create channel. * - Write 0 to ccsr_channel_inst_r and ccsr_channel_r. - * - Call g->ops.channel.bind. + * - Call gm20b_channel_bind and. * - Check that ccsr_channel_inst_r and ccsr_channel_r have * been programmed. * - Check that ch->bound is set. @@ -55,6 +57,31 @@ struct gk20a; int test_gm20b_channel_bind(struct unit_module *m, struct gk20a *g, void *args); + + +/** + * Test specification for: test_gm20b_channel_force_ctx_reload + * + * Description: Force reload of channel context + * + * Test Type: Feature based + * + * Targets: gm20b_channel_force_ctx_reload + * + * Input: test_fifo_init_support() run for this GPU + * + * Steps: + * - Create channel. + * - Write 0 to ccsr_channel_r. + * - Call gm20b_channel_force_ctx_reload + * - Check that ccsr_channel_force_ctx_reload_true_f is set in ccsr_channel_r. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gm20b_channel_force_ctx_reload(struct unit_module *m, + struct gk20a *g, void *args); + + /** * @} */