From 1abed2f6bcb1ed1cbe3e10814e41c4044d2513a4 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Wed, 20 Feb 2019 16:15:35 -0800 Subject: [PATCH] gpu: nvgpu: gr: remove timeslice mode enable check Timeslice mode is always set to enabled. So, it is not required to check for timeslice mode enable and done following cleanup as part of this change. 1. Removed timeslice_mode field from struct gr_gk20a and removed setting of this field from the function gr_gk20a_init_gr_config. 2. Removed checks for timeslice_mode enable in gr_gk20a_commit_global_timeslice function. 3. Removed unused kernel definitions from headers: gr_gpcs_ppcs_cbm_cfg_r() gr_gpcs_ppcs_cbm_cfg_timeslice_mode_enable_v() JIRA NVGPU-2155 Change-Id: Id99f4b771c74f4cea763ea63441043e93def2347 Signed-off-by: Seshendra Gadagottu Change-Id: Id99f4b771c74f4cea763ea63441043e93def2347 Signed-off-by: Seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/2024320 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 43 ++++++------------- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 1 - .../include/nvgpu/hw/gk20a/hw_gr_gk20a.h | 10 +---- 3 files changed, 15 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 7e39ef498..8213fadcb 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -747,7 +747,6 @@ int gr_gk20a_commit_global_ctx_buffers(struct gk20a *g, int gr_gk20a_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c) { - struct gr_gk20a *gr = &g->gr; struct nvgpu_gr_ctx *gr_ctx = NULL; u32 gpm_pd_cfg; u32 pd_ab_dist_cfg0; @@ -763,34 +762,22 @@ int gr_gk20a_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c) ds_debug = gk20a_readl(g, gr_ds_debug_r()); mpc_vtg_debug = gk20a_readl(g, gr_gpcs_tpcs_mpc_vtg_debug_r()); - if (gr->timeslice_mode == gr_gpcs_ppcs_cbm_cfg_timeslice_mode_enable_v()) { - pe_vaf = gk20a_readl(g, gr_gpcs_tpcs_pe_vaf_r()); - pe_vsc_vpc = gk20a_readl(g, gr_gpcs_tpcs_pes_vsc_vpc_r()); + pe_vaf = gk20a_readl(g, gr_gpcs_tpcs_pe_vaf_r()); + pe_vsc_vpc = gk20a_readl(g, gr_gpcs_tpcs_pes_vsc_vpc_r()); - gpm_pd_cfg = gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() | gpm_pd_cfg; - pe_vaf = gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() | pe_vaf; - pe_vsc_vpc = gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() | pe_vsc_vpc; - pd_ab_dist_cfg0 = gr_pd_ab_dist_cfg0_timeslice_enable_en_f() | pd_ab_dist_cfg0; - ds_debug = gr_ds_debug_timeslice_mode_enable_f() | ds_debug; - mpc_vtg_debug = gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() | mpc_vtg_debug; + gpm_pd_cfg = gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() | gpm_pd_cfg; + pe_vaf = gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() | pe_vaf; + pe_vsc_vpc = gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() | pe_vsc_vpc; + pd_ab_dist_cfg0 = gr_pd_ab_dist_cfg0_timeslice_enable_en_f() | pd_ab_dist_cfg0; + ds_debug = gr_ds_debug_timeslice_mode_enable_f() | ds_debug; + mpc_vtg_debug = gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() | mpc_vtg_debug; - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_gpm_pd_cfg_r(), gpm_pd_cfg, false); - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_pe_vaf_r(), pe_vaf, false); - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_pes_vsc_vpc_r(), pe_vsc_vpc, false); - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_pd_ab_dist_cfg0_r(), pd_ab_dist_cfg0, false); - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_ds_debug_r(), ds_debug, false); - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_mpc_vtg_debug_r(), mpc_vtg_debug, false); - } else { - gpm_pd_cfg = gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f() | gpm_pd_cfg; - pd_ab_dist_cfg0 = gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() | pd_ab_dist_cfg0; - ds_debug = gr_ds_debug_timeslice_mode_disable_f() | ds_debug; - mpc_vtg_debug = gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() | mpc_vtg_debug; - - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_gpm_pd_cfg_r(), gpm_pd_cfg, false); - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_pd_ab_dist_cfg0_r(), pd_ab_dist_cfg0, false); - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_ds_debug_r(), ds_debug, false); - nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_mpc_vtg_debug_r(), mpc_vtg_debug, false); - } + nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_gpm_pd_cfg_r(), gpm_pd_cfg, false); + nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_pe_vaf_r(), pe_vaf, false); + nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_pes_vsc_vpc_r(), pe_vsc_vpc, false); + nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_pd_ab_dist_cfg0_r(), pd_ab_dist_cfg0, false); + nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_ds_debug_r(), ds_debug, false); + nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_mpc_vtg_debug_r(), mpc_vtg_debug, false); return 0; } @@ -2389,7 +2376,6 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr) g->ops.gr.bundle_cb_defaults(g); g->ops.gr.cb_size_default(g); g->ops.gr.calc_global_ctx_buffer_size(g); - gr->timeslice_mode = gr_gpcs_ppcs_cbm_cfg_timeslice_mode_enable_v(); nvgpu_log_info(g, "bundle_cb_default_size: %d", gr->bundle_cb_default_size); @@ -2400,7 +2386,6 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr) nvgpu_log_info(g, "attrib_cb_size: %d", gr->attrib_cb_size); nvgpu_log_info(g, "alpha_cb_default_size: %d", gr->alpha_cb_default_size); nvgpu_log_info(g, "alpha_cb_size: %d", gr->alpha_cb_size); - nvgpu_log_info(g, "timeslice_mode: %d", gr->timeslice_mode); return 0; diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 34caeba8a..c4ab028b1 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -273,7 +273,6 @@ struct gr_gk20a { u32 attrib_cb_gfxp_size; u32 alpha_cb_default_size; u32 alpha_cb_size; - u32 timeslice_mode; u32 czf_bypass; u32 pd_max_batches; u32 gfxp_wfi_timeout_count; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h index 8100ca160..569d3d7d7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -3530,14 +3530,6 @@ static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) { return (v & 0x1fU) << 25U; } -static inline u32 gr_gpcs_ppcs_cbm_cfg_r(void) -{ - return 0x0041bec0U; -} -static inline u32 gr_gpcs_ppcs_cbm_cfg_timeslice_mode_enable_v(void) -{ - return 0x00000001U; -} static inline u32 gr_bes_zrop_settings_r(void) { return 0x00408850U;