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gpu: nvgpu: Add flag to map_tiles functions

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Add NVGPU_GRAPHICS flag to support the nvgpu_gr_config_init_map_tiles
and map_tiles related functions and variables.
Use only when this flag is defined.

Jira NVGPU-3583

Change-Id: Ib31a7445bcc573a127d1902bc19fc2aae9548d0f
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130616
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-06-04 16:15:49 -07:00
committed by mobile promotions
parent b127d668ab
commit 1ad54446da
4 changed files with 35 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -408,12 +408,12 @@ static int gr_init_setup_sw(struct gk20a *g)
goto clean_up;
}
#ifdef NVGPU_GRAPHICS
err = nvgpu_gr_config_init_map_tiles(g, gr->config);
if (err != 0) {
goto clean_up;
}
#ifdef NVGPU_GRAPHICS
err = nvgpu_gr_zcull_init(g, &gr->zcull,
nvgpu_gr_falcon_get_zcull_image_size(g->gr->falcon),
g->gr->config);

42
drivers/gpu/nvgpu/common/gr/gr_config.c
View File

@@ -271,6 +271,7 @@ clean_up:
return NULL;
}
#ifdef NVGPU_GRAPHICS
static u32 prime_set[18] = {
2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61 };
@@ -490,18 +491,35 @@ clean_up:
return ret;
}
u32 nvgpu_gr_config_get_max_zcull_per_gpc_count(struct nvgpu_gr_config *config)
{
return config->max_zcull_per_gpc_count;
}
u32 nvgpu_gr_config_get_zcb_count(struct nvgpu_gr_config *config)
{
return config->zcb_count;
}
u32 nvgpu_gr_config_get_gpc_zcb_count(struct nvgpu_gr_config *config,
u32 gpc_index)
{
return config->gpc_zcb_count[gpc_index];
}
#endif
void nvgpu_gr_config_deinit(struct gk20a *g, struct nvgpu_gr_config *config)
{
u32 index;
nvgpu_kfree(g, config->gpc_tpc_count);
#ifdef NVGPU_GRAPHICS
nvgpu_kfree(g, config->gpc_zcb_count);
#endif
nvgpu_kfree(g, config->gpc_ppc_count);
nvgpu_kfree(g, config->gpc_skip_mask);
nvgpu_kfree(g, config->gpc_tpc_mask);
#ifdef NVGPU_GRAPHICS
nvgpu_kfree(g, config->gpc_zcb_count);
nvgpu_kfree(g, config->map_tiles);
#endif
for (index = 0U; index < config->pe_count_per_gpc;
index++) {
nvgpu_kfree(g, config->pes_tpc_count[index]);
@@ -540,24 +558,6 @@ u32 nvgpu_gr_config_get_ppc_count(struct nvgpu_gr_config *config)
return config->ppc_count;
}
#ifdef NVGPU_GRAPHICS
u32 nvgpu_gr_config_get_max_zcull_per_gpc_count(struct nvgpu_gr_config *config)
{
return config->max_zcull_per_gpc_count;
}
u32 nvgpu_gr_config_get_zcb_count(struct nvgpu_gr_config *config)
{
return config->zcb_count;
}
u32 nvgpu_gr_config_get_gpc_zcb_count(struct nvgpu_gr_config *config,
u32 gpc_index)
{
return config->gpc_zcb_count[gpc_index];
}
#endif
u32 nvgpu_gr_config_get_pe_count_per_gpc(struct nvgpu_gr_config *config)
{
return config->pe_count_per_gpc;

17
drivers/gpu/nvgpu/common/gr/gr_config_priv.h
View File

@@ -41,26 +41,16 @@ struct nvgpu_gr_config {
u32 max_gpc_count;
u32 max_tpc_per_gpc_count;
#ifdef NVGPU_GRAPHICS
u32 max_zcull_per_gpc_count;
#endif
u32 max_tpc_count;
u32 gpc_count;
u32 tpc_count;
u32 ppc_count;
#ifdef NVGPU_GRAPHICS
u32 zcb_count;
#endif
u32 pe_count_per_gpc;
u32 sm_count_per_tpc;
u32 *gpc_ppc_count;
u32 *gpc_tpc_count;
#ifdef NVGPU_GRAPHICS
u32 *gpc_zcb_count;
#endif
u32 *pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC];
u32 gpc_mask;
@@ -68,10 +58,15 @@ struct nvgpu_gr_config {
u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC];
u32 *gpc_skip_mask;
#ifdef NVGPU_GRAPHICS
u32 max_zcull_per_gpc_count;
u32 zcb_count;
u32 *gpc_zcb_count;
u8 *map_tiles;
u32 map_tile_count;
u32 map_row_offset;
#endif
u32 no_of_sm;
struct nvgpu_sm_info *sm_to_cluster;
};

14
drivers/gpu/nvgpu/include/nvgpu/gr/config.h
View File

@@ -31,13 +31,6 @@ struct nvgpu_gr_config;
struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g);
void nvgpu_gr_config_deinit(struct gk20a *g, struct nvgpu_gr_config *config);
int nvgpu_gr_config_init_map_tiles(struct gk20a *g,
struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_map_tile_count(struct nvgpu_gr_config *config,
u32 index);
u8 *nvgpu_gr_config_get_map_tiles(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_map_row_offset(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_max_gpc_count(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_max_tpc_per_gpc_count(struct nvgpu_gr_config *config);
@@ -46,7 +39,14 @@ u32 nvgpu_gr_config_get_max_tpc_count(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_gpc_count(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_tpc_count(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_ppc_count(struct nvgpu_gr_config *config);
#ifdef NVGPU_GRAPHICS
int nvgpu_gr_config_init_map_tiles(struct gk20a *g,
struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_map_row_offset(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_map_tile_count(struct nvgpu_gr_config *config,
u32 index);
u8 *nvgpu_gr_config_get_map_tiles(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_max_zcull_per_gpc_count(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_zcb_count(struct nvgpu_gr_config *config);
u32 nvgpu_gr_config_get_gpc_zcb_count(struct nvgpu_gr_config *config,