gpu: nvgpu: simplify gmmu map calls

Introduce nvgpu_gmmu_map_partial() to map a specific size of a buffer
represented by nvgpu_mem, or what nvgpu_gmmu_map() used to do. Delete
the size parameter from nvgpu_gmmu_map() such that it now maps the
entire buffer. The separate size parameter is a historical artifact from
when nvgpu_mem did not exist yet; the typical use is to map the entire
buffer.

Mapping at a certain address with nvgpu_gmmu_map_fixed() still takes the
size parameter.

The returned address still has to be stored somewhere, typically to
mem.gpu_va by the caller so that the matching unmap variant finds the
right address.

Change-Id: I7d67a0b15d741c6bcee1aecff1678e3216cc28d2
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2601788
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/gr/ctx.c

@@ -87,7 +87,6 @@ int nvgpu_gr_ctx_alloc(struct gk20a *g,
 
 	gr_ctx->mem.gpu_va = nvgpu_gmmu_map(vm,
 					&gr_ctx->mem,
-					gr_ctx->mem.size,
 					0, /* not GPU-cacheable */
 					gk20a_mem_flag_none, true,
 					gr_ctx->mem.aperture);
@@ -802,7 +801,7 @@ static int nvgpu_gr_ctx_alloc_ctxsw_buffer(struct vm_gk20a *vm, size_t size,
 		return err;
 	}
 
-	mem->gpu_va = nvgpu_gmmu_map(vm,
+	mem->gpu_va = nvgpu_gmmu_map_partial(vm,
 				mem,
 				mem->aligned_size,
 				NVGPU_VM_MAP_CACHEABLE,
@@ -1004,7 +1003,6 @@ int nvgpu_gr_ctx_alloc_pm_ctx(struct gk20a *g,
 
 	pm_ctx->mem.gpu_va = nvgpu_gmmu_map(vm,
 					&pm_ctx->mem,
-					pm_ctx->mem.size,
 					NVGPU_VM_MAP_CACHEABLE,
 					gk20a_mem_flag_none, true,
 					pm_ctx->mem.aperture);

drivers/gpu/nvgpu/common/gr/global_ctx.c

@@ -326,7 +326,7 @@ u64 nvgpu_gr_global_ctx_buffer_map(struct nvgpu_gr_global_ctx_buffer_desc *desc,
 		return 0;
 	}
 
-	gpu_va = nvgpu_gmmu_map(vm, &desc[index].mem, desc[index].mem.size,
+	gpu_va = nvgpu_gmmu_map(vm, &desc[index].mem,
 			flags, gk20a_mem_flag_none, priv,
 			desc[index].mem.aperture);
 	return gpu_va;

drivers/gpu/nvgpu/common/gr/gr_falcon.c

@@ -225,7 +225,6 @@ static int nvgpu_gr_falcon_init_ctxsw_ucode_vaspace(struct gk20a *g,
 	/* Map ucode surface to GMMU */
 	ucode_info->surface_desc.gpu_va = nvgpu_gmmu_map(vm,
 					&ucode_info->surface_desc,
-					ucode_info->surface_desc.size,
 					0, /* flags */
 					gk20a_mem_flag_read_only,
 					false,

drivers/gpu/nvgpu/common/gr/subctx.c

@@ -51,7 +51,6 @@ struct nvgpu_gr_subctx *nvgpu_gr_subctx_alloc(struct gk20a *g,
 
 	subctx->ctx_header.gpu_va = nvgpu_gmmu_map(vm,
 				&subctx->ctx_header,
-				subctx->ctx_header.size,
 				0, /* not GPU-cacheable */
 				gk20a_mem_flag_none, true,
 				subctx->ctx_header.aperture);

drivers/gpu/nvgpu/common/mm/dma.c

@@ -158,7 +158,7 @@ int nvgpu_dma_alloc_map_flags_sys(struct vm_gk20a *vm, unsigned long flags,
 		return err;
 	}
 
-	mem->gpu_va = nvgpu_gmmu_map(vm, mem, size, 0,
+	mem->gpu_va = nvgpu_gmmu_map(vm, mem, 0,
 				     gk20a_mem_flag_none, false,
 				     mem->aperture);
 	if (mem->gpu_va == 0ULL) {
@@ -190,7 +190,7 @@ int nvgpu_dma_alloc_map_flags_vid(struct vm_gk20a *vm, unsigned long flags,
 		return err;
 	}
 
-	mem->gpu_va = nvgpu_gmmu_map(vm, mem, size, 0,
+	mem->gpu_va = nvgpu_gmmu_map(vm, mem, 0,
 				     gk20a_mem_flag_none, false,
 				     mem->aperture);
 	if (mem->gpu_va == 0ULL) {

drivers/gpu/nvgpu/common/mm/gmmu/page_table.c

@@ -131,7 +131,7 @@ static u64 nvgpu_gmmu_map_core(struct vm_gk20a *vm,
 /*
  * Map a nvgpu_mem into the GMMU. This is for kernel space to use.
  */
-u64 nvgpu_gmmu_map(struct vm_gk20a *vm,
+u64 nvgpu_gmmu_map_partial(struct vm_gk20a *vm,
 		   struct nvgpu_mem *mem,
 		   u64 size,
 		   u32 flags,
@@ -143,6 +143,20 @@ u64 nvgpu_gmmu_map(struct vm_gk20a *vm,
 				   aperture);
 }
 
+/*
+ * Map a nvgpu_mem into the GMMU. This is for kernel space to use.
+ */
+u64 nvgpu_gmmu_map(struct vm_gk20a *vm,
+		   struct nvgpu_mem *mem,
+		   u32 flags,
+		   enum gk20a_mem_rw_flag rw_flag,
+		   bool priv,
+		   enum nvgpu_aperture aperture)
+{
+	return nvgpu_gmmu_map_core(vm, mem, 0, mem->size, flags, rw_flag, priv,
+				   aperture);
+}
+
 /*
  * Like nvgpu_gmmu_map() except this can work on a fixed address.
  */

drivers/gpu/nvgpu/common/semaphore/semaphore_pool.c

@@ -135,7 +135,7 @@ int nvgpu_semaphore_pool_map(struct nvgpu_semaphore_pool *p,
 		goto fail_unmap;
 	}
 
-	addr = nvgpu_gmmu_map(vm, &p->rw_mem, SZ_4K, 0,
+	addr = nvgpu_gmmu_map_partial(vm, &p->rw_mem, SZ_4K, 0,
 			      gk20a_mem_flag_none, 0,
 			      p->rw_mem.aperture);
 

drivers/gpu/nvgpu/hal/sync/syncpt_cmdbuf_gv11b_fusa.c

@@ -42,7 +42,7 @@ static int set_syncpt_ro_map_gpu_va_locked(struct vm_gk20a *vm)
 		return 0;
 	}
 
-	vm->syncpt_ro_map_gpu_va = nvgpu_gmmu_map(vm,
+	vm->syncpt_ro_map_gpu_va = nvgpu_gmmu_map_partial(vm,
 			&g->syncpt_mem, g->syncpt_unit_size,
 			0, gk20a_mem_flag_read_only,
 			false, APERTURE_SYSMEM);
@@ -85,7 +85,7 @@ int gv11b_syncpt_alloc_buf(struct nvgpu_channel *c,
 		return err;
 	}
 
-	syncpt_buf->gpu_va = nvgpu_gmmu_map(c->vm, syncpt_buf,
+	syncpt_buf->gpu_va = nvgpu_gmmu_map_partial(c->vm, syncpt_buf,
 			g->syncpt_size, 0, gk20a_mem_flag_none,
 			false, APERTURE_SYSMEM);
 

drivers/gpu/nvgpu/include/nvgpu/gmmu.h

@@ -281,8 +281,8 @@ int nvgpu_gmmu_init_page_table(struct vm_gk20a *vm);
  * context on the GR, CE to access the given virtual address.
  *
  * @param vm		[in]	Pointer to virtual memory structure.
- * @param mem		[in]	Structure for storing the memory informati on.
+ * @param mem		[in]	The previously allocated buffer to map.
- * @param size		[in]	Size of the buffer in bytes.
+ * @param size		[in]	Size of the mapping in bytes.
  * @param flags		[in]	Mapping flags.
  *                              - Min: NVGPU_VM_MAP_FIXED_OFFSET
  *                              - Max: NVGPU_VM_MAP_PLATFORM_ATOMIC
@@ -311,6 +311,8 @@ int nvgpu_gmmu_init_page_table(struct vm_gk20a *vm);
  * Invalidates the GPU TLB, gm20b_fb_tlb_invalidate does the tlb invalidate.
  * Release the VM GMMU lock.
  *
+ * Note that mem->gpu_va is not updated.
+ *
  * @return	valid GMMU VA start address in case of success.
  * @retval	0 in case of all possible failures.
  * 		Possible Failure cases:
@@ -320,7 +322,7 @@ int nvgpu_gmmu_init_page_table(struct vm_gk20a *vm);
  * 			- invalid inputs.
  *
  */
-u64 nvgpu_gmmu_map(struct vm_gk20a *vm,
+u64 nvgpu_gmmu_map_partial(struct vm_gk20a *vm,
 		   struct nvgpu_mem *mem,
 		   u64 size,
 		   u32 flags,
@@ -328,6 +330,19 @@ u64 nvgpu_gmmu_map(struct vm_gk20a *vm,
 		   bool priv,
 		   enum nvgpu_aperture aperture);
 
+/**
+ * @brief Map a whole buffer into the GMMU.
+ *
+ * This is like nvgpu_gmmu_map_partial() but with the full requested size of
+ * the buffer in nvgpu_mem.size.
+ */
+u64 nvgpu_gmmu_map(struct vm_gk20a *vm,
+		   struct nvgpu_mem *mem,
+		   u32 flags,
+		   enum gk20a_mem_rw_flag rw_flag,
+		   bool priv,
+		   enum nvgpu_aperture aperture);
+
 /**
  * @brief Map memory into the GMMU at a fixed address. This is required to
  * make the parrticular context on the GR, CE to access the given virtual

drivers/gpu/nvgpu/os/linux/cde.c

@@ -1411,7 +1411,6 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
 
 	/* map backing store to gpu virtual space */
 	vaddr = nvgpu_gmmu_map(ch->vm, &cbc->compbit_store.mem,
-			       cbc->compbit_store.mem.size,
 			       NVGPU_VM_MAP_CACHEABLE,
 			       gk20a_mem_flag_read_only,
 			       false,

drivers/gpu/nvgpu/os/linux/linux-channel.c

@@ -530,7 +530,7 @@ static int nvgpu_channel_alloc_usermode_buffers(struct nvgpu_channel *c,
 	}
 
 	c->usermode_gpfifo.gpu_va = nvgpu_gmmu_map(c->vm, &c->usermode_gpfifo,
-			c->usermode_gpfifo.size, 0, gk20a_mem_flag_read_only,
+			0, gk20a_mem_flag_read_only,
 			false, c->usermode_gpfifo.aperture);
 
 	if (c->usermode_gpfifo.gpu_va == 0) {

libs/dgpu/libnvgpu-drv-dgpu_safe.export

@@ -406,8 +406,9 @@ nvgpu_get_pte
 nvgpu_gmmu_default_big_page_size
 nvgpu_gmmu_init_page_table
 nvgpu_gmmu_map
-nvgpu_gmmu_map_locked
 nvgpu_gmmu_map_fixed
+nvgpu_gmmu_map_locked
+nvgpu_gmmu_map_partial
 nvgpu_gmmu_unmap
 nvgpu_gmmu_unmap_addr
 nvgpu_gmmu_unmap_locked

libs/igpu/libnvgpu-drv-igpu_safe.export

@@ -422,8 +422,9 @@ nvgpu_get_pte
 nvgpu_gmmu_default_big_page_size
 nvgpu_gmmu_init_page_table
 nvgpu_gmmu_map
-nvgpu_gmmu_map_locked
 nvgpu_gmmu_map_fixed
+nvgpu_gmmu_map_locked
+nvgpu_gmmu_map_partial
 nvgpu_gmmu_unmap
 nvgpu_gmmu_unmap_addr
 nvgpu_gmmu_unmap_locked

userspace/units/mm/gmmu/page_table/page_table.c

@@ -479,7 +479,7 @@ int test_nvgpu_gmmu_map_unmap(struct unit_module *m, struct gk20a *g,
 				params->flags, params->rw_flag, params->priv,
 				params->aperture);
 	} else {
-		mem.gpu_va = nvgpu_gmmu_map(g->mm.pmu.vm, &mem, mem.size,
+		mem.gpu_va = nvgpu_gmmu_map(g->mm.pmu.vm, &mem,
 				params->flags, params->rw_flag, params->priv,
 				params->aperture);
 	}
@@ -607,7 +607,7 @@ int test_nvgpu_gmmu_map_unmap_map_fail(struct unit_module *m, struct gk20a *g,
 		g->ops.fb.tlb_invalidate = hal_fb_tlb_invalidate_fail;
 	}
 
-	mem.gpu_va = nvgpu_gmmu_map(g->mm.pmu.vm, &mem, mem.size,
+	mem.gpu_va = nvgpu_gmmu_map(g->mm.pmu.vm, &mem,
 				NVGPU_VM_MAP_CACHEABLE, gk20a_mem_flag_none,
 				true, APERTURE_SYSMEM);
 
@@ -656,7 +656,7 @@ int test_nvgpu_gmmu_set_pte(struct unit_module *m, struct gk20a *g, void *args)
 	p->mm_is_iommuable = params->is_iommuable;
 	mem.size = TEST_SIZE;
 	mem.cpu_va = (void *) TEST_PA_ADDRESS;
-	mem.gpu_va = nvgpu_gmmu_map(g->mm.pmu.vm, &mem, mem.size,
+	mem.gpu_va = nvgpu_gmmu_map(g->mm.pmu.vm, &mem,
 			params->flags, params->rw_flag, params->priv,
 			params->aperture);
 
@@ -1053,7 +1053,7 @@ int test_nvgpu_page_table_c1_full(struct unit_module *m, struct gk20a *g,
 				&test_iommu_sysmem, NULL, vm, mixed_sgt);
 		} else {
 			mem[mem_i].gpu_va = nvgpu_gmmu_map(vm, &mem[mem_i],
-				mem[mem_i].size, NVGPU_VM_MAP_CACHEABLE,
+				NVGPU_VM_MAP_CACHEABLE,
 				gk20a_mem_flag_none, true, APERTURE_SYSMEM);
 		}
 

userspace/units/sync/nvgpu-sync.c

@@ -348,7 +348,7 @@ int test_sync_get_ro_map(struct unit_module *m, struct gk20a *g, void *args)
 
 	for (branches = 0U; branches <= F_SYNC_GET_RO_MAP_MAX; branches++) {
 		if (branches == F_SYNC_GET_RO_MAP_PRE_ALLOCATED) {
-			ch->vm->syncpt_ro_map_gpu_va = nvgpu_gmmu_map(ch->vm,
+			ch->vm->syncpt_ro_map_gpu_va = nvgpu_gmmu_map_partial(ch->vm,
 					&g->syncpt_mem, g->syncpt_unit_size,
 					0, gk20a_mem_flag_read_only,
 					false, APERTURE_SYSMEM);