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gpu: nvgpu: Set DMA mask on a per-platform basis

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Each GPU platform has different DMA limitations. For older
chips the maximum size of a DMA buffer was more limited than
newer SoCs (read: Xavier) and discrete GPUs.

This patch adds support to set the DMA mask for a GPU on a
per platform basis by adding a platform field that is populated
with the maximum allowed DMA mask. That mask is programmed by
the driver common code. If no mask is specified then the
default mask size is 16GB (34 bits).

Bug 2043276

Change-Id: I9c3c76c86bac6c485eb1197326e662516fbcaa41
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700980
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2018-04-23 12:28:09 -07:00
committed by Tejal Kudav
parent 1e889871bc
commit 1b71581b9e
6 changed files with 27 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/nvgpu/common/linux/driver_common.c
View File

@@ -73,9 +73,15 @@ static void nvgpu_init_vars(struct gk20a *g)
dev->dma_parms = &l->dma_parms;
dma_set_max_seg_size(dev, UINT_MAX);
/* 34 bit mask - can be expanded for later chips is needed. */
dma_set_mask(dev, DMA_BIT_MASK(34));
dma_set_coherent_mask(dev, DMA_BIT_MASK(34));
/*
* A default of 16GB is the largest supported DMA size that is
* acceptable to all currently supported Tegra SoCs.
*/
if (!platform->dma_mask)
platform->dma_mask = DMA_BIT_MASK(34);
dma_set_mask(dev, platform->dma_mask);
dma_set_coherent_mask(dev, platform->dma_mask);
nvgpu_init_list_node(&g->profiler_objects);

9
drivers/gpu/nvgpu/common/linux/pci.c
View File

@@ -101,6 +101,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ch_wdt_timeout_ms = 7000,
.honors_aperture = true,
.dma_mask = DMA_BIT_MASK(40),
.vbios_min_version = 0x86063000,
.hardcode_sw_threshold = true,
.ina3221_dcb_index = 0,
@@ -137,6 +138,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ch_wdt_timeout_ms = 7000,
.honors_aperture = true,
.dma_mask = DMA_BIT_MASK(40),
.vbios_min_version = 0x86062d00,
.hardcode_sw_threshold = true,
.ina3221_dcb_index = 0,
@@ -173,6 +175,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ch_wdt_timeout_ms = 7000,
.honors_aperture = true,
.dma_mask = DMA_BIT_MASK(40),
.vbios_min_version = 0x86063000,
.hardcode_sw_threshold = true,
.ina3221_dcb_index = 0,
@@ -209,6 +212,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ch_wdt_timeout_ms = 7000,
.honors_aperture = true,
.dma_mask = DMA_BIT_MASK(40),
.vbios_min_version = 0x86065300,
.hardcode_sw_threshold = false,
.ina3221_dcb_index = 1,
@@ -245,6 +249,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ch_wdt_timeout_ms = 7000,
.honors_aperture = true,
.dma_mask = DMA_BIT_MASK(40),
.vbios_min_version = 0x88001e00,
.hardcode_sw_threshold = false,
.run_preos = true,
@@ -279,6 +284,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ch_wdt_timeout_ms = 7000,
.honors_aperture = true,
.dma_mask = DMA_BIT_MASK(40),
.vbios_min_version = 0x88001e00,
.hardcode_sw_threshold = false,
.run_preos = true,
@@ -313,6 +319,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ch_wdt_timeout_ms = 7000,
.honors_aperture = true,
.dma_mask = DMA_BIT_MASK(40),
.vbios_min_version = 0x88000126,
.hardcode_sw_threshold = false,
.run_preos = true,
@@ -348,6 +355,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ch_wdt_timeout_ms = 7000,
.honors_aperture = true,
.dma_mask = DMA_BIT_MASK(40),
.vbios_min_version = 0x1,
.hardcode_sw_threshold = false,
.run_preos = true,
@@ -386,6 +394,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.ch_wdt_timeout_ms = 30000,
.honors_aperture = true,
.dma_mask = DMA_BIT_MASK(40),
.vbios_min_version = 0x1,
.hardcode_sw_threshold = false,
.unified_memory = false,

6
drivers/gpu/nvgpu/common/linux/platform_gk20a.h
View File

@@ -242,6 +242,12 @@ struct gk20a_platform {
/* unified or split memory with separate vidmem? */
bool unified_memory;
/*
* DMA mask for Linux (both coh and non-coh). If not set defaults to
* 0x3ffffffff (i.e a 34 bit mask).
*/
u64 dma_mask;
/* minimum supported VBIOS version */
u32 vbios_min_version;

1
drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c
View File

@@ -951,6 +951,7 @@ struct gk20a_platform gm20b_tegra_platform = {
.soc_name = "tegra21x",
.unified_memory = true,
.dma_mask = DMA_BIT_MASK(34),
.secure_buffer_size = 335872,
};

1
drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
View File

@@ -438,6 +438,7 @@ struct gk20a_platform gp10b_tegra_platform = {
.soc_name = "tegra18x",
.unified_memory = true,
.dma_mask = DMA_BIT_MASK(36),
.ltc_streamid = TEGRA_SID_GPUB,

1
drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c
View File

@@ -237,6 +237,7 @@ struct gk20a_platform gv11b_tegra_platform = {
.honors_aperture = true,
.unified_memory = true,
.dma_mask = DMA_BIT_MASK(36),
.reset_assert = gp10b_tegra_reset_assert,
.reset_deassert = gp10b_tegra_reset_deassert,