gpu: nvgpu: gv11b: init and implement reset_enable_hw

-implement gv11b specific reset_enable_hw fifo ops

-timeout period in fifo_fb_timeout_r() is set to init instead of max
This register specifies the number of microseconds Host
should wait for a response from FB before initiating a timeout interrupt.
For bringup, this value should be set to a lower value than usual, such as
~.5 milliseconds (500), to help find out bugs in the memory subsystem.

-timeout period in pbdma_timeout_r() is set to init instead of max
This register contains a value used for detecting timeouts.
The timeout value is in microsecond ticks.
The timeouts that use this value are:
GPfifo fetch timeouts to FB for acks, reqs, rdats.
PBDMA connection to LB.
GPfifo processor timeouts to FB for acks, reqs, rdats.
Method processor timeouts to FB for acks, reqs, rdats.
The init value is changed to 64K us based on bug 1816557.

JIRA GPUT19X-74
JIRA GPUT19X-47

Change-Id: I6f818e129c3ea67571d206c5e735607cbfcf6ec6
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1325352
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/gv11b/fifo_gv11b.c

@@ -29,6 +29,7 @@
 #include <nvgpu/hw/gv11b/hw_usermode_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_top_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
 
 #include "fifo_gv11b.h"
 #include "subctx_gv11b.h"
@@ -684,6 +685,92 @@ static void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
 		pbdma_intr_0_device_pending_f();
 }
 
+static u32 gv11b_fifo_intr_0_en_mask(struct gk20a *g)
+{
+	u32 intr_0_en_mask;
+
+	intr_0_en_mask = g->ops.fifo.intr_0_error_mask(g);
+
+	intr_0_en_mask |= fifo_intr_0_runlist_event_pending_f() |
+				 fifo_intr_0_pbdma_intr_pending_f();
+
+	return intr_0_en_mask;
+}
+
+int gv11b_init_fifo_reset_enable_hw(struct gk20a *g)
+{
+	u32 intr_stall;
+	u32 mask;
+	u32 timeout;
+	unsigned int i;
+	u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
+
+	gk20a_dbg_fn("");
+
+	/* enable pmc pfifo */
+	g->ops.mc.reset(g, mc_enable_pfifo_enabled_f());
+
+	if (g->ops.clock_gating.slcg_ce2_load_gating_prod)
+		g->ops.clock_gating.slcg_ce2_load_gating_prod(g,
+				g->slcg_enabled);
+	if (g->ops.clock_gating.slcg_fifo_load_gating_prod)
+		g->ops.clock_gating.slcg_fifo_load_gating_prod(g,
+				g->slcg_enabled);
+	if (g->ops.clock_gating.blcg_fifo_load_gating_prod)
+		g->ops.clock_gating.blcg_fifo_load_gating_prod(g,
+				g->blcg_enabled);
+
+	/* enable pbdma */
+	mask = 0;
+	for (i = 0; i < host_num_pbdma; ++i)
+		mask |= mc_enable_pb_sel_f(mc_enable_pb_0_enabled_v(), i);
+	gk20a_writel(g, mc_enable_pb_r(), mask);
+
+
+	timeout = gk20a_readl(g, fifo_fb_timeout_r());
+	timeout = set_field(timeout, fifo_fb_timeout_period_m(),
+			fifo_fb_timeout_period_init_f());
+	gk20a_dbg_info("fifo_fb_timeout reg val = 0x%08x", timeout);
+	gk20a_writel(g, fifo_fb_timeout_r(), timeout);
+
+	/* write pbdma timeout value */
+	for (i = 0; i < host_num_pbdma; i++) {
+		timeout = gk20a_readl(g, pbdma_timeout_r(i));
+		timeout = set_field(timeout, pbdma_timeout_period_m(),
+				    pbdma_timeout_period_init_f());
+		gk20a_dbg_info("pbdma_timeout reg val = 0x%08x", timeout);
+		gk20a_writel(g, pbdma_timeout_r(i), timeout);
+	}
+	/* clear and enable pbdma interrupt */
+	for (i = 0; i < host_num_pbdma; i++) {
+		gk20a_writel(g, pbdma_intr_0_r(i), 0xFFFFFFFF);
+		gk20a_writel(g, pbdma_intr_1_r(i), 0xFFFFFFFF);
+
+		intr_stall = gk20a_readl(g, pbdma_intr_stall_r(i));
+		gk20a_dbg_info("pbdma id:%u, intr_en_0 0x%08x", i, intr_stall);
+		gk20a_writel(g, pbdma_intr_en_0_r(i), intr_stall);
+
+		intr_stall = gk20a_readl(g, pbdma_intr_stall_1_r(i));
+		gk20a_dbg_info("pbdma id:%u, intr_en_1 0x%08x", i, intr_stall);
+		gk20a_writel(g, pbdma_intr_en_1_r(i), intr_stall);
+	}
+
+	/* clear runlist interrupts */
+	gk20a_writel(g, fifo_intr_runlist_r(), ~0);
+
+	/* clear and enable pfifo interrupt */
+	gk20a_writel(g, fifo_intr_0_r(), 0xFFFFFFFF);
+	mask = gv11b_fifo_intr_0_en_mask(g);
+	gk20a_dbg_info("fifo_intr_en_0 0x%08x", mask);
+	gk20a_writel(g, fifo_intr_en_0_r(), mask);
+	gk20a_dbg_info("fifo_intr_en_1 = 0x80000000");
+	gk20a_writel(g, fifo_intr_en_1_r(), 0x80000000);
+
+	gk20a_dbg_fn("done");
+
+	return 0;
+}
+
 void gv11b_init_fifo(struct gpu_ops *gops)
 {
 	gp10b_init_fifo(gops);
@@ -712,4 +799,5 @@ void gv11b_init_fifo(struct gpu_ops *gops)
 	gops->fifo.is_preempt_pending = gv11b_fifo_is_preempt_pending;
 	gops->fifo.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg;
 	gops->fifo.init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs;
+	gops->fifo.reset_enable_hw = gv11b_init_fifo_reset_enable_hw;
 }

drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h

@@ -298,6 +298,10 @@ static inline u32 fifo_fb_timeout_period_max_f(void)
 {
 	return 0x3fffffff;
 }
+static inline u32 fifo_fb_timeout_period_init_f(void)
+{
+	return 0x3c00;
+}
 static inline u32 fifo_sched_disable_r(void)
 {
 	return 0x00002630;

drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h

@@ -618,4 +618,20 @@ static inline u32 pbdma_set_channel_info_veid_f(u32 v)
 {
 	return (v & 0x3f) << 8;
 }
+static inline u32 pbdma_timeout_r(u32 i)
+{
+	return 0x0004012c + i*8192;
+}
+static inline u32 pbdma_timeout_period_m(void)
+{
+	return 0xffffffff << 0;
+}
+static inline u32 pbdma_timeout_period_max_f(void)
+{
+	return 0xffffffff;
+}
+static inline u32 pbdma_timeout_period_init_f(void)
+{
+	return 0x10000;
+}
 #endif