diff --git a/userspace/units/fifo/pbdma/gm20b/nvgpu-pbdma-gm20b.c b/userspace/units/fifo/pbdma/gm20b/nvgpu-pbdma-gm20b.c
index 6f22e1725..376e1a5cf 100644
--- a/userspace/units/fifo/pbdma/gm20b/nvgpu-pbdma-gm20b.c
+++ b/userspace/units/fifo/pbdma/gm20b/nvgpu-pbdma-gm20b.c
@@ -444,7 +444,9 @@ int test_gm20b_pbdma_get_userd(struct unit_module *m,
 			pbdma_userd_hi_addr_f(addr_hi), goto done);
 
 	mem.aperture = APERTURE_INVALID;
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, true);
 	err = EXPECT_BUG(mask = gm20b_pbdma_get_userd_aperture_mask(g, &mem));
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, false);
 	unit_assert(err != 0, goto done);
 	unit_assert(mask == 0xaaaa, goto done);
 
diff --git a/userspace/units/gr/falcon/nvgpu-gr-falcon.c b/userspace/units/gr/falcon/nvgpu-gr-falcon.c
index d783996b5..327272804 100644
--- a/userspace/units/gr/falcon/nvgpu-gr-falcon.c
+++ b/userspace/units/gr/falcon/nvgpu-gr-falcon.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -177,10 +177,12 @@ static int gr_falcon_bind_instblk(struct unit_module *m, struct gk20a *g)
 	/* Generate expected bug with hi32 instr value */
 	mem = &ucode_info->inst_blk_desc;
 	mem->cpu_va = (void *)0xFFFFFFFFFFFFFFFF;
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, true);
 	if (!EXPECT_BUG(nvgpu_gr_falcon_init_ctxsw(g, unit_gr_falcon))) {
 		unit_return_fail(m,
 			"falcon_init_ctxsw test1 failed\n");
 	}
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, false);
 	mem->cpu_va = NULL;
 
 	err = nvgpu_alloc_inst_block(g, &ucode_info->inst_blk_desc);
diff --git a/userspace/units/mm/nvgpu_mem/nvgpu_mem.c b/userspace/units/mm/nvgpu_mem/nvgpu_mem.c
index 1f965da91..056013b15 100644
--- a/userspace/units/mm/nvgpu_mem/nvgpu_mem.c
+++ b/userspace/units/mm/nvgpu_mem/nvgpu_mem.c
@@ -256,6 +256,8 @@ int test_nvgpu_aperture_mask(struct unit_module *m,
 	}
 #endif
 
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, true);
+
 	/* Case: APERTURE_INVALID */
 	test_mem->aperture = APERTURE_INVALID;
 	if (!EXPECT_BUG(nvgpu_aperture_mask(g, test_mem, sysmem_mask,
@@ -272,6 +274,8 @@ int test_nvgpu_aperture_mask(struct unit_module *m,
 			"did not BUG() for junk aperture as expected\n");
 	}
 
+	nvgpu_set_enabled(g, NVGPU_MM_HONORS_APERTURE, false);
+
 	/* Reset attributes */
 	test_mem->aperture = APERTURE_SYSMEM;