nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-22 09:12:24 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: update dma_mask based on H/W compatibility

Browse Source 
To be able to access the full physical memory range, gpu's dma_mask
needs to be set to the max value of H/W compatible range.

For example. In order to support from 2GB to 66 GB, GV11B's dma_mask
needs to be atleast 37 bits. Set GV11B's dma_mask to 38 bit
and T23X's dma_mask to 39 bit. These values are supported by H/W

Bug 3656729

Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: Icfff3c36a8c9cf074a254fa773c42e18020ae5de
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2723640
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Brad Griffis <bgriffis@nvidia.com>
This commit is contained in:
Debarshi Dutta
2022-06-02 10:56:02 +05:30
committed by mobile promotions
parent b8b90f85ee
commit 1bf9309f17
2 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/os/linux/platform_ga10b_tegra.c
View File

@@ -765,7 +765,7 @@ struct gk20a_platform ga10b_tegra_platform = {
* This specifies the maximum contiguous size of a DMA mapping to Linux * This specifies the maximum contiguous size of a DMA mapping to Linux
* kernel's DMA framework. * kernel's DMA framework.
* The IOMMU is capable of mapping all of physical memory and hence * The IOMMU is capable of mapping all of physical memory and hence
* dma_mask is set to memory size (128GB in this case). * dma_mask is set to memory size (512GB in this case).
* For iGPU, nvgpu executes own dma allocs (e.g. alloc_page()) and * For iGPU, nvgpu executes own dma allocs (e.g. alloc_page()) and
* sg_table construction. No IOMMU mapping is required and so dma_mask * sg_table construction. No IOMMU mapping is required and so dma_mask
* value is not important. * value is not important.
@@ -773,7 +773,7 @@ struct gk20a_platform ga10b_tegra_platform = {
* significant. In this case, IOMMU bit in GPU physical address is not * significant. In this case, IOMMU bit in GPU physical address is not
* relevant. * relevant.
*/ */
.dma_mask = DMA_BIT_MASK(37), .dma_mask = DMA_BIT_MASK(39),
.reset_assert = gp10b_tegra_reset_assert, .reset_assert = gp10b_tegra_reset_assert,
.reset_deassert = gp10b_tegra_reset_deassert, .reset_deassert = gp10b_tegra_reset_deassert,

4
drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
View File

@@ -1,7 +1,7 @@
/* /*
* GV11B Tegra Platform Interface * GV11B Tegra Platform Interface
* *
* Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -307,7 +307,7 @@ struct gk20a_platform gv11b_tegra_platform = {
.honors_aperture = true, .honors_aperture = true,
.unified_memory = true, .unified_memory = true,
.dma_mask = DMA_BIT_MASK(36), .dma_mask = DMA_BIT_MASK(38),
.reset_assert = gp10b_tegra_reset_assert, .reset_assert = gp10b_tegra_reset_assert,
.reset_deassert = gp10b_tegra_reset_deassert, .reset_deassert = gp10b_tegra_reset_deassert,