diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c
index a21cc31ec..9fc5fdcd0 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c
@@ -80,14 +80,21 @@ static u32 mc_gp10b_intr_pending_f(struct gk20a *g, u32 unit)
 	return intr_pending_f;
 }
 
+static void mc_gp10b_isr_stall_primary(struct gk20a *g, u32 mc_intr_0)
+{
+	if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) {
+		g->ops.bus.isr(g);
+	}
+	if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) {
+		g->ops.priv_ring.isr(g);
+	}
+}
+
 static void mc_gp10b_isr_stall_secondary_1(struct gk20a *g, u32 mc_intr_0)
 {
 	if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) {
 		g->ops.mc.ltc_isr(g);
 	}
-	if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) {
-		g->ops.bus.isr(g);
-	}
 #ifdef CONFIG_NVGPU_DGPU
 	if ((g->ops.mc.is_intr_nvlink_pending != NULL) &&
 			g->ops.mc.is_intr_nvlink_pending(g, mc_intr_0)) {
@@ -112,9 +119,6 @@ static void mc_gp10b_isr_stall_secondary_0(struct gk20a *g, u32 mc_intr_0)
 	if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) {
 		g->ops.pmu.pmu_isr(g);
 	}
-	if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) {
-		g->ops.priv_ring.isr(g);
-	}
 }
 
 static void mc_gp10b_isr_stall_engine(struct gk20a *g,
@@ -186,6 +190,8 @@ void mc_gp10b_isr_stall(struct gk20a *g)
 
 	nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x", mc_intr_0);
 
+	mc_gp10b_isr_stall_primary(g, mc_intr_0);
+
 	for (i = 0U; i < g->fifo.num_engines; i++) {
 		engine_id = g->fifo.active_engines_list[i];