From 1cd29cc075c85d5fff8f982c7cf5aa461b412922 Mon Sep 17 00:00:00 2001 From: Vinod G Date: Mon, 6 May 2019 15:28:50 -0700 Subject: [PATCH] gpu: nvgpu: Fix MISRA Rule 15.7 errors in gr/intr unit Fix MISRA violations for Rule 15.7 in gr/intr unit misra_violation: No non-empty terminating "else" statement. Jira NVGPU-3227 Change-Id: I369aa2997dc3f45f6ff3946a2febfc0a95a47d34 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/2113223 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c | 14 ++++++++------ drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c | 14 ++++++++------ 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c index a99b3fef4..d45c6e084 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c @@ -136,12 +136,14 @@ void gv11b_gr_intr_set_skedcheck(struct gk20a *g, u32 data) gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(), gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f() ); - } else if ((data & NVC397_SET_SKEDCHECK_18_MASK) == - NVC397_SET_SKEDCHECK_18_ENABLE) { - reg_val = set_field(reg_val, - gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(), - gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f() - ); + } else { + if ((data & NVC397_SET_SKEDCHECK_18_MASK) == + NVC397_SET_SKEDCHECK_18_ENABLE) { + reg_val = set_field(reg_val, + gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(), + gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f() + ); + } } nvgpu_log_info(g, "sked_hww_esr_en = 0x%x", reg_val); nvgpu_writel(g, gr_sked_hww_esr_en_r(), reg_val); diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c index f4b3be550..836fc45ed 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c @@ -46,12 +46,14 @@ static void gr_tu104_set_sm_disp_ctrl(struct gk20a *g, u32 data) gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_m(), gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_disable_f() ); - } else if ((data & NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_MASK) - == NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_ENABLE) { - reg_val = set_field(reg_val, - gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_m(), - gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_enable_f() - ); + } else { + if ((data & NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_MASK) + == NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_ENABLE) { + reg_val = set_field(reg_val, + gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_m(), + gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_enable_f() + ); + } } nvgpu_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), reg_val);