gpu: nvgpu: introduce nvgpu_enable_irqs

Prepare function to enable the stall and non-stall kernel interrupts.
Update the type of irq state irqs_enabled to bool.

JIRA NVGPU-1592

Change-Id: I758794e0f230814a0bea2f3c035562e9a5c7e0ea
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203859
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-09-23 12:31:30 +05:30
committed by Alex Waterman
parent 99ffa2622c
commit 1cd6ae945c
4 changed files with 38 additions and 11 deletions

View File

@@ -1850,7 +1850,7 @@ struct gk20a {
struct nvgpu_cond sw_irq_nonstall_last_handled_cond; struct nvgpu_cond sw_irq_nonstall_last_handled_cond;
nvgpu_atomic_t sw_irq_nonstall_last_handled; nvgpu_atomic_t sw_irq_nonstall_last_handled;
int irqs_enabled; bool irqs_enabled;
u32 irq_stall; /* can be same as irq_nonstall in case of PCI */ u32 irq_stall; /* can be same as irq_nonstall in case of PCI */
u32 irq_nonstall; u32 irq_nonstall;

View File

@@ -136,6 +136,15 @@ void nvgpu_sw_quiesce(struct gk20a *g);
*/ */
void nvgpu_start_gpu_idle(struct gk20a *g); void nvgpu_start_gpu_idle(struct gk20a *g);
/**
* @brief Enable interrupt handlers
*
* @param g [in] The GPU
*
* Enable interrupt handlers.
*/
int nvgpu_enable_irqs(struct gk20a *g);
/** /**
* @brief Disable interrupt handlers * @brief Disable interrupt handlers
* *

View File

@@ -487,10 +487,11 @@ int gk20a_pm_finalize_poweron(struct device *dev)
trace_gk20a_finalize_poweron_done(dev_name(dev)); trace_gk20a_finalize_poweron_done(dev_name(dev));
#endif #endif
enable_irq(g->irq_stall); err = nvgpu_enable_irqs(g);
if (g->irq_stall != g->irq_nonstall) if (err) {
enable_irq(g->irq_nonstall); nvgpu_err(g, "failed to enable irqs %d", err);
g->irqs_enabled = 1; goto done;
}
gk20a_scale_resume(dev_from_gk20a(g)); gk20a_scale_resume(dev_from_gk20a(g));
@@ -534,13 +535,25 @@ static int gk20a_lockout_registers(struct gk20a *g)
return 0; return 0;
} }
int nvgpu_enable_irqs(struct gk20a *g)
{
if (!g->irqs_enabled) {
enable_irq(g->irq_stall);
if (g->irq_stall != g->irq_nonstall)
enable_irq(g->irq_nonstall);
g->irqs_enabled = true;
}
return 0;
}
void nvgpu_disable_irqs(struct gk20a *g) void nvgpu_disable_irqs(struct gk20a *g)
{ {
if (g->irqs_enabled) { if (g->irqs_enabled) {
disable_irq(g->irq_stall); disable_irq(g->irq_stall);
if (g->irq_stall != g->irq_nonstall) if (g->irq_stall != g->irq_nonstall)
disable_irq(g->irq_nonstall); disable_irq(g->irq_nonstall);
g->irqs_enabled = 0; g->irqs_enabled = false;
} }
} }
@@ -552,7 +565,7 @@ static int gk20a_pm_prepare_poweroff(struct device *dev)
#endif #endif
struct gk20a_platform *platform = gk20a_get_platform(dev); struct gk20a_platform *platform = gk20a_get_platform(dev);
bool irqs_enabled; bool irqs_enabled;
int ret = 0; int ret = 0, err = 0;
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
@@ -589,10 +602,10 @@ static int gk20a_pm_prepare_poweroff(struct device *dev)
error: error:
/* re-enabled IRQs if previously enabled */ /* re-enabled IRQs if previously enabled */
if (irqs_enabled) { if (irqs_enabled) {
enable_irq(g->irq_stall); err = nvgpu_enable_irqs(g);
if (g->irq_stall != g->irq_nonstall) if (err) {
enable_irq(g->irq_nonstall); nvgpu_err(g, "failed to enable irqs %d", err);
g->irqs_enabled = 1; }
} }
gk20a_scale_resume(dev); gk20a_scale_resume(dev);

View File

@@ -63,6 +63,11 @@ void nvgpu_start_gpu_idle(struct gk20a *g)
nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true); nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
} }
int nvgpu_enable_irqs(struct gk20a *g)
{
return 0;
}
void nvgpu_disable_irqs(struct gk20a *g) void nvgpu_disable_irqs(struct gk20a *g)
{ {
} }