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gpu: nvgpu: introduce nvgpu_enable_irqs
Prepare function to enable the stall and non-stall kernel interrupts. Update the type of irq state irqs_enabled to bool. JIRA NVGPU-1592 Change-Id: I758794e0f230814a0bea2f3c035562e9a5c7e0ea Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2203859 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Philip Elcan <pelcan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
committed by
Alex Waterman
parent
99ffa2622c
commit
1cd6ae945c
@@ -1850,7 +1850,7 @@ struct gk20a {
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struct nvgpu_cond sw_irq_nonstall_last_handled_cond;
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struct nvgpu_cond sw_irq_nonstall_last_handled_cond;
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nvgpu_atomic_t sw_irq_nonstall_last_handled;
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nvgpu_atomic_t sw_irq_nonstall_last_handled;
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int irqs_enabled;
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bool irqs_enabled;
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u32 irq_stall; /* can be same as irq_nonstall in case of PCI */
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u32 irq_stall; /* can be same as irq_nonstall in case of PCI */
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u32 irq_nonstall;
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u32 irq_nonstall;
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@@ -136,6 +136,15 @@ void nvgpu_sw_quiesce(struct gk20a *g);
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*/
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*/
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void nvgpu_start_gpu_idle(struct gk20a *g);
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void nvgpu_start_gpu_idle(struct gk20a *g);
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/**
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* @brief Enable interrupt handlers
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*
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* @param g [in] The GPU
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*
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* Enable interrupt handlers.
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*/
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int nvgpu_enable_irqs(struct gk20a *g);
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/**
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/**
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* @brief Disable interrupt handlers
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* @brief Disable interrupt handlers
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*
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*
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@@ -487,10 +487,11 @@ int gk20a_pm_finalize_poweron(struct device *dev)
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trace_gk20a_finalize_poweron_done(dev_name(dev));
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trace_gk20a_finalize_poweron_done(dev_name(dev));
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#endif
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#endif
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enable_irq(g->irq_stall);
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err = nvgpu_enable_irqs(g);
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if (g->irq_stall != g->irq_nonstall)
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if (err) {
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enable_irq(g->irq_nonstall);
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nvgpu_err(g, "failed to enable irqs %d", err);
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g->irqs_enabled = 1;
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goto done;
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}
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gk20a_scale_resume(dev_from_gk20a(g));
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gk20a_scale_resume(dev_from_gk20a(g));
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@@ -534,13 +535,25 @@ static int gk20a_lockout_registers(struct gk20a *g)
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return 0;
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return 0;
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}
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}
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int nvgpu_enable_irqs(struct gk20a *g)
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{
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if (!g->irqs_enabled) {
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enable_irq(g->irq_stall);
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if (g->irq_stall != g->irq_nonstall)
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enable_irq(g->irq_nonstall);
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g->irqs_enabled = true;
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}
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return 0;
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}
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void nvgpu_disable_irqs(struct gk20a *g)
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void nvgpu_disable_irqs(struct gk20a *g)
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{
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{
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if (g->irqs_enabled) {
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if (g->irqs_enabled) {
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disable_irq(g->irq_stall);
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disable_irq(g->irq_stall);
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if (g->irq_stall != g->irq_nonstall)
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if (g->irq_stall != g->irq_nonstall)
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disable_irq(g->irq_nonstall);
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disable_irq(g->irq_nonstall);
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g->irqs_enabled = 0;
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g->irqs_enabled = false;
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}
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}
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}
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}
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@@ -552,7 +565,7 @@ static int gk20a_pm_prepare_poweroff(struct device *dev)
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#endif
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#endif
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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bool irqs_enabled;
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bool irqs_enabled;
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int ret = 0;
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int ret = 0, err = 0;
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nvgpu_log_fn(g, " ");
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nvgpu_log_fn(g, " ");
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@@ -589,10 +602,10 @@ static int gk20a_pm_prepare_poweroff(struct device *dev)
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error:
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error:
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/* re-enabled IRQs if previously enabled */
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/* re-enabled IRQs if previously enabled */
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if (irqs_enabled) {
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if (irqs_enabled) {
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enable_irq(g->irq_stall);
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err = nvgpu_enable_irqs(g);
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if (g->irq_stall != g->irq_nonstall)
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if (err) {
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enable_irq(g->irq_nonstall);
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nvgpu_err(g, "failed to enable irqs %d", err);
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g->irqs_enabled = 1;
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}
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}
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}
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gk20a_scale_resume(dev);
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gk20a_scale_resume(dev);
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@@ -63,6 +63,11 @@ void nvgpu_start_gpu_idle(struct gk20a *g)
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nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
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nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
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}
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}
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int nvgpu_enable_irqs(struct gk20a *g)
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{
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return 0;
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}
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void nvgpu_disable_irqs(struct gk20a *g)
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void nvgpu_disable_irqs(struct gk20a *g)
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{
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{
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}
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}
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