gpu: nvgpu: falcon interface/HAL update

- Add methods to read/write falcon mailbox
at interface layer
- Created falcon mailbox read/write HAL
- Added HAL methods to read/write mailbox
- Added macro to get next block based on address
- Added macro to get IMEM tag using IMEM address
- Added ucode header format

Change-Id: I879b1df4538d403cac40fd4ed6e723190f62922c
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
(cherry picked from commit 30e8b76a7be9d9e6d8225bdc08e441f408692f63)
Reviewed-on: https://git-master.nvidia.com/r/1509469
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/include/nvgpu/falcon.h

@@ -79,6 +79,15 @@
 #define FALCON_REG_RSVD2	(31)
 #define FALCON_REG_SIZE		(32)
 
+#define FALCON_MAILBOX_COUNT 0x02
+#define FALCON_BLOCK_SIZE 0x100
+
+#define GET_IMEM_TAG(IMEM_ADDR) (IMEM_ADDR >> 8)
+
+#define GET_NEXT_BLOCK(ADDR) \
+	((((ADDR + (FALCON_BLOCK_SIZE - 1)) & ~(FALCON_BLOCK_SIZE-1)) \
+		/ FALCON_BLOCK_SIZE) << 8)
+
 /*
  * Falcon HWCFG request read types defines
  */
@@ -113,6 +122,33 @@ enum flcn_mem_type {
 	MEM_IMEM
 };
 
+/* Falcon ucode header format
+ * OS Code Offset
+ * OS Code Size
+ * OS Data Offset
+ * OS Data Size
+ * NumApps (N)
+ * App   0 Code Offset
+ * App   0 Code Size
+ * .  .  .  .
+ * App   N - 1 Code Offset
+ * App   N - 1 Code Size
+ * App   0 Data Offset
+ * App   0 Data Size
+ * .  .  .  .
+ * App   N - 1 Data Offset
+ * App   N - 1 Data Size
+ * OS Ovl Offset
+ * OS Ovl Size
+*/
+#define OS_CODE_OFFSET 0x0
+#define OS_CODE_SIZE   0x1
+#define OS_DATA_OFFSET 0x2
+#define OS_DATA_SIZE   0x3
+#define NUM_APPS       0x4
+#define APP_0_CODE_OFFSET 0x5
+#define APP_0_CODE_SIZE   0x6
+
 struct nvgpu_falcon_dma_info {
 	u32 fb_base;
 	u32 fb_off;