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gpu: nvgpu: Remove pmgr.h dependency from gk20a.h

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gk20a.h depends on definition of struct pmgr_pmupstate. Change that
to a pointer and use forward declaration, and allocation and
free functions. Also set pointer to NULL when freed.

Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.

JIRA NVGPU-596

Change-Id: I21ff1ae93ac7b92a71502f97785252c04964e72f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1954003
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2018-11-09 08:46:44 -08:00
committed by mobile promotions
parent ae6e4d0572
commit 1cf6e4fc5e
11 changed files with 111 additions and 71 deletions
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27
drivers/gpu/nvgpu/pmgr/pwrmonitor.c
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@@ -27,6 +27,7 @@
#include <nvgpu/string.h>
#include "pwrdev.h"
#include "pmgr.h"
#include "gp106/bios_gp106.h"
static int _pwr_channel_pmudata_instget(struct gk20a *g,
@@ -85,7 +86,7 @@ static u32 _pwr_channel_state_init(struct gk20a *g)
u8 indx = 0;
struct pwr_channel *pchannel;
u32 objmask =
g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super.objmask;
g->pmgr_pmu->pmgr_monitorobjs.pwr_channels.super.objmask;
/* Initialize each PWR_CHANNEL's dependent channel mask */
BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK(32, indx, objmask) {
@@ -214,7 +215,7 @@ static int devinit_get_pwr_topology_table(struct gk20a *g,
goto done;
}
g->pmgr_pmu.pmgr_monitorobjs.b_is_topology_tbl_ver_1x = false;
g->pmgr_pmu->pmgr_monitorobjs.b_is_topology_tbl_ver_1x = false;
if (pwr_topology_table_header.header_size <
VBIOS_POWER_TOPOLOGY_2X_HEADER_SIZE_06) {
@@ -312,7 +313,7 @@ int pmgr_monitor_sw_setup(struct gk20a *g)
/* Construct the Super Class and override the Interfaces */
status = boardobjgrpconstruct_e32(g,
&g->pmgr_pmu.pmgr_monitorobjs.pwr_channels);
&g->pmgr_pmu->pmgr_monitorobjs.pwr_channels);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for pmgr channel, status - 0x%x",
@@ -320,14 +321,14 @@ int pmgr_monitor_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &(g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super);
pboardobjgrp = &(g->pmgr_pmu->pmgr_monitorobjs.pwr_channels.super);
/* Override the Interfaces */
pboardobjgrp->pmudatainstget = _pwr_channel_pmudata_instget;
/* Construct the Super Class and override the Interfaces */
status = boardobjgrpconstruct_e32(g,
&g->pmgr_pmu.pmgr_monitorobjs.pwr_ch_rels);
&g->pmgr_pmu->pmgr_monitorobjs.pwr_ch_rels);
if (status != 0) {
nvgpu_err(g,
"error creating boardobjgrp for pmgr channel relationship, status - 0x%x",
@@ -335,20 +336,20 @@ int pmgr_monitor_sw_setup(struct gk20a *g)
goto done;
}
pboardobjgrp = &(g->pmgr_pmu.pmgr_monitorobjs.pwr_ch_rels.super);
pboardobjgrp = &(g->pmgr_pmu->pmgr_monitorobjs.pwr_ch_rels.super);
/* Override the Interfaces */
pboardobjgrp->pmudatainstget = _pwr_channel_rels_pmudata_instget;
/* Initialize the Total GPU Power Channel Mask to 0 */
g->pmgr_pmu.pmgr_monitorobjs.pmu_data.channels.hdr.data.total_gpu_power_channel_mask = 0;
g->pmgr_pmu.pmgr_monitorobjs.total_gpu_channel_idx =
g->pmgr_pmu->pmgr_monitorobjs.pmu_data.channels.hdr.data.total_gpu_power_channel_mask = 0;
g->pmgr_pmu->pmgr_monitorobjs.total_gpu_channel_idx =
CTRL_PMGR_PWR_CHANNEL_INDEX_INVALID;
/* Supported topology table version 1.0 */
g->pmgr_pmu.pmgr_monitorobjs.b_is_topology_tbl_ver_1x = true;
g->pmgr_pmu->pmgr_monitorobjs.b_is_topology_tbl_ver_1x = true;
ppwrmonitorobjs = &(g->pmgr_pmu.pmgr_monitorobjs);
ppwrmonitorobjs = &(g->pmgr_pmu->pmgr_monitorobjs);
status = devinit_get_pwr_topology_table(g, ppwrmonitorobjs);
if (status != 0) {
@@ -361,14 +362,14 @@ int pmgr_monitor_sw_setup(struct gk20a *g)
}
/* Initialise physicalChannelMask */
g->pmgr_pmu.pmgr_monitorobjs.physical_channel_mask = 0;
g->pmgr_pmu->pmgr_monitorobjs.physical_channel_mask = 0;
pboardobjgrp = &g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super;
pboardobjgrp = &g->pmgr_pmu->pmgr_monitorobjs.pwr_channels.super;
BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct pwr_channel *, pchannel, indx) {
if (_pwr_channel_implements(pchannel,
CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR)) {
g->pmgr_pmu.pmgr_monitorobjs.physical_channel_mask |= BIT(indx);
g->pmgr_pmu->pmgr_monitorobjs.physical_channel_mask |= BIT(indx);
}
}