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gpu: nvgpu: introduce internal runlist domain

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The current runlist code assumes a single runlist buffer to hold all TSG
and channel entries. Create separate RL domain and domain memory types
to hold data that is related to only a scheduling domain and not
directly to the runlist hardware; in the future, more than one domains
may exist and one of them is enabled at a time.

The domain is used only internally by the runlist code at this point and
is functionally equivalent to the current runlist memory that houses the
round robin entries.

The double buffering is still kept, although more domains might benefit
from some cleverness. Although any number of created domains may be
edited in runtime, nly one runlist memory is accessed by the hardware at
a time. To spare some contiguous memory, this should be considered an
opportunity for optimization in the future.

Jira NVGPU-6425

Change-Id: Id99c55f058ad56daa48b732240f05b3195debfb1
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2618386
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Hölttä
2021-10-28 22:10:34 +03:00
committed by mobile promotions
parent e616b2ba4d
commit 1d23b8f13a
13 changed files with 195 additions and 120 deletions
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6
userspace/units/fifo/runlist/gk20a/nvgpu-runlist-gk20a.c
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@@ -75,17 +75,19 @@ done:
int test_gk20a_runlist_hw_submit(struct unit_module *m,
struct gk20a *g, void *args)
{
struct nvgpu_fifo *f = &g->fifo;
int ret = UNIT_FAIL;
u32 runlist_id = nvgpu_engine_get_gr_runlist_id(g);
u32 count;
u32 buffer_index = 0;
for (count = 0; count < 2; count++) {
nvgpu_writel(g, fifo_runlist_r(), 0);
nvgpu_writel(g, fifo_runlist_base_r(), 0);
gk20a_runlist_hw_submit(g, runlist_id, count, buffer_index);
f->runlists[runlist_id]->domain->mem_hw->count = count;
gk20a_runlist_hw_submit(g, f->runlists[runlist_id]);
if (count == 0) {
unit_assert(nvgpu_readl(g, fifo_runlist_base_r()) == 0,
goto done);