gpu: nvgpu: set GR tick frequency to max

GR tick frequency needs to be set to MAX value for profiler
use cases for gp10b/gv11b/tu104 chips.

Add new HAL g->ops.ptimer.config_gr_tick_freq() that configures GR
tick frequency to MAX value and call this HAL in GPU poweron path.

This support is not needed in safety build, so compile everything
only if CONFIG_NVGPU_DEBUGGER is enabled

Bug 200289214

Change-Id: Id8378540cc67ca0041b56990f8676e3a105403a5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195163
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

arch/nvgpu-hal-new.yaml

@@ -88,12 +88,18 @@ priv_ring:
   owner: Seema K
   sources: [ hal/priv_ring/priv_ring_gm20b.c ]
 
-ptimer:
+ptimer_fusa:
   safe: yes
   owner: Terje B
   sources: [ hal/ptimer/ptimer_gk20a_fusa.c,
              hal/ptimer/ptimer_gk20a.h ]
 
+ptimer:
+  safe: no
+  owner: Deepak N
+  sources: [ hal/ptimer/ptimer_gp10b.c,
+             hal/ptimer/ptimer_gp10b.h ]
+
 cg_fusa:
   safe: yes
   owner: Seema K

drivers/gpu/nvgpu/Makefile

@@ -650,6 +650,7 @@ nvgpu-y += \
 	hal/priv_ring/priv_ring_gm20b_fusa.o \
 	hal/priv_ring/priv_ring_gp10b_fusa.o \
 	hal/ptimer/ptimer_gk20a_fusa.o \
+	hal/ptimer/ptimer_gp10b.o \
 	hal/sync/syncpt_cmdbuf_gv11b_fusa.o \
 	hal/therm/therm_gm20b_fusa.o \
 	hal/therm/therm_gv11b_fusa.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -351,6 +351,7 @@ srcs += common/debugger.c \
 	hal/gr/ctxsw_prog/ctxsw_prog_gm20b_dbg.c \
 	hal/gr/hwpm_map/hwpm_map_gv100.c \
 	hal/ltc/ltc_gm20b_dbg.c \
+	hal/ptimer/ptimer_gp10b.c \
 	hal/perf/perf_gv11b.c \
 	hal/gr/gr/gr_gk20a.c \
 	hal/gr/gr/gr_gm20b.c \

drivers/gpu/nvgpu/common/init/nvgpu_init.c

@@ -382,6 +382,12 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 		}
 	}
 
+#ifdef CONFIG_NVGPU_DEBUGGER
+	if (g->ops.ptimer.config_gr_tick_freq != NULL) {
+		g->ops.ptimer.config_gr_tick_freq(g);
+	}
+#endif
+
 	if (g->ops.fb.mem_unlock != NULL && !g->is_fusa_sku) {
 		err = g->ops.fb.mem_unlock(g);
 		if (err != 0) {

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -83,6 +83,7 @@
 #include "hal/fuse/fuse_gm20b.h"
 #include "hal/fuse/fuse_gp10b.h"
 #include "hal/ptimer/ptimer_gk20a.h"
+#include "hal/ptimer/ptimer_gp10b.h"
 #include "hal/regops/regops_gp10b.h"
 #include "hal/fifo/fifo_gk20a.h"
 #include "hal/fifo/preempt_gk20a.h"
@@ -1109,6 +1110,9 @@ static const struct gpu_ops gp10b_ops = {
 		.read_ptimer = gk20a_read_ptimer,
 #ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+		.config_gr_tick_freq = gp10b_ptimer_config_gr_tick_freq,
 #endif
 	},
 #if defined(CONFIG_NVGPU_CYCLESTATS)

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -80,6 +80,7 @@
 #include "hal/fuse/fuse_gm20b.h"
 #include "hal/fuse/fuse_gp10b.h"
 #include "hal/ptimer/ptimer_gk20a.h"
+#include "hal/ptimer/ptimer_gp10b.h"
 #include "hal/regops/regops_gv11b.h"
 #ifdef CONFIG_NVGPU_RECOVERY
 #include "hal/rc/rc_gv11b.h"
@@ -1311,6 +1312,9 @@ static const struct gpu_ops gv11b_ops = {
 		.read_ptimer = gk20a_read_ptimer,
 #ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+		.config_gr_tick_freq = gp10b_ptimer_config_gr_tick_freq,
 #endif
 	},
 #if defined(CONFIG_NVGPU_CYCLESTATS)

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -68,6 +68,7 @@
 #include "hal/fb/fb_mmu_fault_tu104.h"
 #include "hal/fb/intr/fb_intr_tu104.h"
 #include "hal/ptimer/ptimer_gk20a.h"
+#include "hal/ptimer/ptimer_gp10b.h"
 #include "hal/regops/regops_tu104.h"
 #include "hal/fuse/fuse_gm20b.h"
 #include "hal/fuse/fuse_gp10b.h"
@@ -1334,6 +1335,9 @@ static const struct gpu_ops tu104_ops = {
 		.read_ptimer = gk20a_read_ptimer,
 #ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
 		.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+		.config_gr_tick_freq = gp10b_ptimer_config_gr_tick_freq,
 #endif
 	},
 #if defined(CONFIG_NVGPU_CYCLESTATS)

drivers/gpu/nvgpu/hal/ptimer/ptimer_gp10b.c

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/io.h>
+
+#include "ptimer_gp10b.h"
+
+#include <nvgpu/hw/gp10b/hw_timer_gp10b.h>
+
+void gp10b_ptimer_config_gr_tick_freq(struct gk20a *g)
+{
+	nvgpu_writel(g, timer_gr_tick_freq_r(),
+		timer_gr_tick_freq_select_f(
+			timer_gr_tick_freq_select_max_f()));
+}

drivers/gpu/nvgpu/hal/ptimer/ptimer_gp10b.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef PTIMER_GP10B_H
+#define PTIMER_GP10B_H
+
+#ifdef CONFIG_NVGPU_DEBUGGER
+
+struct gk20a;
+
+void gp10b_ptimer_config_gr_tick_freq(struct gk20a *g);
+
+#endif /* CONFIG_NVGPU_DEBUGGER */
+#endif /* PTIMER_GP10B_H */

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1713,6 +1713,9 @@ struct gpu_ops {
 		int (*get_timestamps_zipper)(struct gk20a *g,
 			u32 source_id, u32 count,
 			struct nvgpu_cpu_time_correlation_sample *samples);
+#endif
+#ifdef CONFIG_NVGPU_DEBUGGER
+		void (*config_gr_tick_freq)(struct gk20a *g);
 #endif
 	} ptimer;
 

drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h

@@ -76,4 +76,7 @@
 #define timer_pri_timeout_fecs_errcode_r()                         (0x0000908cU)
 #define timer_time_0_r()                                           (0x00009400U)
 #define timer_time_1_r()                                           (0x00009410U)
+#define timer_gr_tick_freq_r()                                     (0x00009480U)
+#define timer_gr_tick_freq_select_f(v)                   ((U32(v) & 0x7U) << 0U)
+#define timer_gr_tick_freq_select_max_f()                                 (0x0U)
 #endif

drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h

@@ -76,4 +76,7 @@
 #define timer_pri_timeout_fecs_errcode_r()                         (0x0000908cU)
 #define timer_time_0_r()                                           (0x00009400U)
 #define timer_time_1_r()                                           (0x00009410U)
+#define timer_gr_tick_freq_r()                                     (0x00009480U)
+#define timer_gr_tick_freq_select_f(v)                   ((U32(v) & 0x7U) << 0U)
+#define timer_gr_tick_freq_select_max_f()                                 (0x0U)
 #endif

drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_timer_tu104.h

@@ -73,4 +73,7 @@
 #define timer_pri_timeout_fecs_errcode_r()                         (0x0000908cU)
 #define timer_time_0_r()                                           (0x00009400U)
 #define timer_time_1_r()                                           (0x00009410U)
+#define timer_gr_tick_freq_r()                                     (0x00009480U)
+#define timer_gr_tick_freq_select_f(v)                   ((U32(v) & 0x7U) << 0U)
+#define timer_gr_tick_freq_select_max_f()                                 (0x0U)
 #endif