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gpu: nvgpu: Update PMU firmware version.

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This patch also updates PMU cmdline args as
required by updated firmware.

GPUT19x-30

Change-Id: I44214007046081a44acc7284eb2854d0548a8da8
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1498188
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This commit is contained in:
Deepak Goyal
2017-06-08 11:21:52 +05:30
committed by mobile promotions
parent 0ad7f1d9aa
commit 1dfcf1833b
4 changed files with 19 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
View File

@@ -205,6 +205,11 @@ static u32 pmu_cmdline_size_v5(struct nvgpu_pmu *pmu)
return sizeof(struct pmu_cmdline_args_v5);
}
static u32 pmu_cmdline_size_v6(struct nvgpu_pmu *pmu)
{
return sizeof(struct pmu_cmdline_args_v6);
}
static void set_pmu_cmdline_args_cpufreq_v5(struct nvgpu_pmu *pmu, u32 freq)
{
pmu->args_v5.cpu_freq_hz = 204000000;
@@ -1586,7 +1591,7 @@ int gk20a_init_pmu(struct nvgpu_pmu *pmu)
g->ops.pmu_ver.cmd_id_zbc_table_update = 16;
g->ops.pmu_ver.is_pmu_zbc_save_supported = false;
g->ops.pmu_ver.get_pmu_cmdline_args_size =
pmu_cmdline_size_v5;
pmu_cmdline_size_v6;
g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
set_pmu_cmdline_args_cpufreq_v5;
g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode =

2
drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
View File

@@ -30,7 +30,7 @@ struct nvgpu_firmware;
#define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe)
#define APP_VERSION_NC_3 21688026
#define APP_VERSION_NC_3 22204331
#define APP_VERSION_NC_2 20429989
#define APP_VERSION_NC_1 20313802
#define APP_VERSION_NC_0 20360931

1
drivers/gpu/nvgpu/include/nvgpu/pmu.h
View File

@@ -314,6 +314,7 @@ struct nvgpu_pmu {
struct pmu_cmdline_args_v3 args_v3;
struct pmu_cmdline_args_v4 args_v4;
struct pmu_cmdline_args_v5 args_v5;
struct pmu_cmdline_args_v6 args_v6;
};
unsigned long perfmon_events_cnt;
bool perfmon_sampling_enabled;

11
drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h
View File

@@ -77,6 +77,17 @@ struct pmu_cmdline_args_v5 {
u32 dummy;
};
struct pmu_cmdline_args_v6 {
u32 cpu_freq_hz;
struct flcn_mem_desc_v0 trace_buf;
u8 secure_mode;
u8 raise_priv_sec;
struct flcn_mem_desc_v0 gc6_ctx;
struct flcn_mem_desc_v0 gc6_bsod_ctx;
struct flcn_mem_desc_v0 init_data_dma_info;
u32 dummy;
};
/* GPU ID */
#define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2
#define PMU_SHA1_GID_SIGNATURE_SIZE 4