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gpu: nvgpu: Fix MISRA 21.2 violations in log.h
MISRA 21.2 prohibits naming functions with double underscore. So, rename __nvgpu_log_dbg() and __nvgpu_log_msg() to nvgpu_log_dbg_impl() and nvgpu_log_msg_impl(), respectively. JIRA NVGPU-3368 Change-Id: I4548820f6772875088d095539b6da92051e08653 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2118043 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -40,11 +40,11 @@ enum nvgpu_log_type {
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* of printing data to a UART, log, whatever.
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* of printing data to a UART, log, whatever.
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*/
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*/
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__attribute__((format (printf, 5, 6)))
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__attribute__((format (printf, 5, 6)))
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void __nvgpu_log_msg(struct gk20a *g, const char *func_name, int line,
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void nvgpu_log_msg_impl(struct gk20a *g, const char *func_name, int line,
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enum nvgpu_log_type type, const char *fmt, ...);
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enum nvgpu_log_type type, const char *fmt, ...);
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__attribute__((format (printf, 5, 6)))
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__attribute__((format (printf, 5, 6)))
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void __nvgpu_log_dbg(struct gk20a *g, u64 log_mask,
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void nvgpu_log_dbg_impl(struct gk20a *g, u64 log_mask,
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const char *func_name, int line,
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const char *func_name, int line,
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const char *fmt, ...);
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const char *fmt, ...);
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@@ -109,7 +109,7 @@ bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask);
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* Print a message if the log_mask matches the enabled debugging.
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* Print a message if the log_mask matches the enabled debugging.
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*/
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*/
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#define nvgpu_log(g, log_mask, fmt, arg...) \
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#define nvgpu_log(g, log_mask, fmt, arg...) \
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__nvgpu_log_dbg(g, log_mask, __func__, __LINE__, fmt, ##arg)
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nvgpu_log_dbg_impl(g, log_mask, __func__, __LINE__, fmt, ##arg)
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/**
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/**
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* nvgpu_err - Print an error
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* nvgpu_err - Print an error
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@@ -121,7 +121,7 @@ bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask);
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* Uncondtionally print an error message.
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* Uncondtionally print an error message.
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*/
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*/
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#define nvgpu_err(g, fmt, arg...) \
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#define nvgpu_err(g, fmt, arg...) \
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__nvgpu_log_msg(g, __func__, __LINE__, NVGPU_ERROR, fmt, ##arg)
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nvgpu_log_msg_impl(g, __func__, __LINE__, NVGPU_ERROR, fmt, ##arg)
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/**
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/**
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* nvgpu_err - Print a warning
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* nvgpu_err - Print a warning
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@@ -133,7 +133,7 @@ bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask);
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* Uncondtionally print a warming message.
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* Uncondtionally print a warming message.
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*/
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*/
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#define nvgpu_warn(g, fmt, arg...) \
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#define nvgpu_warn(g, fmt, arg...) \
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__nvgpu_log_msg(g, __func__, __LINE__, NVGPU_WARNING, fmt, ##arg)
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nvgpu_log_msg_impl(g, __func__, __LINE__, NVGPU_WARNING, fmt, ##arg)
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/**
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/**
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* nvgpu_info - Print an info message
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* nvgpu_info - Print an info message
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@@ -145,7 +145,7 @@ bool nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask);
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* Unconditionally print an information message.
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* Unconditionally print an information message.
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*/
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*/
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#define nvgpu_info(g, fmt, arg...) \
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#define nvgpu_info(g, fmt, arg...) \
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__nvgpu_log_msg(g, __func__, __LINE__, NVGPU_INFO, fmt, ##arg)
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nvgpu_log_msg_impl(g, __func__, __LINE__, NVGPU_INFO, fmt, ##arg)
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/*
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/*
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* Some convenience macros.
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* Some convenience macros.
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@@ -172,7 +172,7 @@ extern u64 nvgpu_dbg_mask;
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#define gk20a_dbg(log_mask, fmt, arg...) \
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#define gk20a_dbg(log_mask, fmt, arg...) \
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do { \
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do { \
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if (((log_mask) & nvgpu_dbg_mask) != 0) { \
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if (((log_mask) & nvgpu_dbg_mask) != 0) { \
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__nvgpu_log_msg(NULL, __func__, __LINE__, \
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nvgpu_log_msg_impl(NULL, __func__, __LINE__, \
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NVGPU_DEBUG, fmt "\n", ##arg); \
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NVGPU_DEBUG, fmt "\n", ##arg); \
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} \
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} \
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} while (false)
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} while (false)
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@@ -1,7 +1,5 @@
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# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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__nvgpu_log_dbg
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__nvgpu_log_msg
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bitmap_clear
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bitmap_clear
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bitmap_find_next_zero_area_off
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bitmap_find_next_zero_area_off
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bitmap_set
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bitmap_set
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@@ -88,6 +86,8 @@ nvgpu_kmem_cache_destroy
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nvgpu_kmem_cache_free
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nvgpu_kmem_cache_free
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nvgpu_kmem_get_fault_injection
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nvgpu_kmem_get_fault_injection
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nvgpu_kzalloc_impl
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nvgpu_kzalloc_impl
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nvgpu_log_dbg_impl
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nvgpu_log_msg_impl
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nvgpu_memset
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nvgpu_memset
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nvgpu_mem_create_from_phys
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nvgpu_mem_create_from_phys
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nvgpu_mem_iommu_translate
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nvgpu_mem_iommu_translate
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@@ -93,7 +93,7 @@ static void __dma_dbg(struct gk20a *g, size_t size, unsigned long flags,
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nvgpu_dma_flags_to_str(g, flags, flags_str);
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nvgpu_dma_flags_to_str(g, flags, flags_str);
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__nvgpu_log_dbg(g, gpu_dbg_dma,
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nvgpu_log_dbg_impl(g, gpu_dbg_dma,
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func, line,
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func, line,
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"DMA %s: [%s] size=%-7zu "
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"DMA %s: [%s] size=%-7zu "
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"aligned=%-7zu total=%-10llukB %s",
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"aligned=%-7zu total=%-10llukB %s",
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* under the terms and conditions of the GNU General Public License,
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@@ -98,7 +98,7 @@ static void __nvgpu_really_print_log(u32 trace, const char *gpu_name,
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}
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}
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__attribute__((format (printf, 5, 6)))
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__attribute__((format (printf, 5, 6)))
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void __nvgpu_log_msg(struct gk20a *g, const char *func_name, int line,
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void nvgpu_log_msg_impl(struct gk20a *g, const char *func_name, int line,
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enum nvgpu_log_type type, const char *fmt, ...)
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enum nvgpu_log_type type, const char *fmt, ...)
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{
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{
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char log[LOG_BUFFER_LENGTH];
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char log[LOG_BUFFER_LENGTH];
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@@ -113,7 +113,7 @@ void __nvgpu_log_msg(struct gk20a *g, const char *func_name, int line,
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}
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}
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__attribute__((format (printf, 5, 6)))
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__attribute__((format (printf, 5, 6)))
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void __nvgpu_log_dbg(struct gk20a *g, u64 log_mask,
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void nvgpu_log_dbg_impl(struct gk20a *g, u64 log_mask,
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const char *func_name, int line,
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const char *func_name, int line,
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const char *fmt, ...)
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const char *fmt, ...)
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{
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{
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@@ -28,5 +28,5 @@ int nvgpu_current_pid(struct gk20a *g)
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void nvgpu_print_current_impl(struct gk20a *g, const char *func_name, int line,
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void nvgpu_print_current_impl(struct gk20a *g, const char *func_name, int line,
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void *ctx, enum nvgpu_log_type type)
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void *ctx, enum nvgpu_log_type type)
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{
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{
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__nvgpu_log_msg(g, func_name, line, type, current->comm);
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nvgpu_log_msg_impl(g, func_name, line, type, current->comm);
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}
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}
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@@ -66,7 +66,7 @@ static void __nvgpu_really_print_log(const char *gpu_name,
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}
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}
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__attribute__((format (printf, 5, 6)))
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__attribute__((format (printf, 5, 6)))
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void __nvgpu_log_msg(struct gk20a *g, const char *func_name, int line,
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void nvgpu_log_msg_impl(struct gk20a *g, const char *func_name, int line,
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enum nvgpu_log_type type, const char *fmt, ...)
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enum nvgpu_log_type type, const char *fmt, ...)
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{
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{
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char log[LOG_BUFFER_LENGTH];
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char log[LOG_BUFFER_LENGTH];
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@@ -81,7 +81,7 @@ void __nvgpu_log_msg(struct gk20a *g, const char *func_name, int line,
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}
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}
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__attribute__((format (printf, 5, 6)))
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__attribute__((format (printf, 5, 6)))
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void __nvgpu_log_dbg(struct gk20a *g, u64 log_mask,
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void nvgpu_log_dbg_impl(struct gk20a *g, u64 log_mask,
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const char *func_name, int line,
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const char *func_name, int line,
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const char *fmt, ...)
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const char *fmt, ...)
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{
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{
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@@ -52,8 +52,10 @@ void nvgpu_print_current_impl(struct gk20a *g, const char *func_name, int line,
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/* pthread_getname_np() will return null terminated string on success */
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/* pthread_getname_np() will return null terminated string on success */
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if (pthread_getname_np(0, current_tname, CURRENT_NAME_LEN) == 0) {
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if (pthread_getname_np(0, current_tname, CURRENT_NAME_LEN) == 0) {
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__nvgpu_log_msg(g, func_name, line, type, "%s", current_tname);
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nvgpu_log_msg_impl(g, func_name, line, type, "%s",
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current_tname);
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} else {
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} else {
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__nvgpu_log_msg(g, func_name, line, type, "(unknown process)");
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nvgpu_log_msg_impl(g, func_name, line, type,
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"(unknown process)");
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}
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}
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}
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}
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