From 1eb8abe0de6059b39bd4920c8bdf96419b8f8cb3 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Tue, 9 Apr 2019 19:30:39 +0530 Subject: [PATCH] gpu: nvgpu: fix MISRA rule 5.7 and 4.7 violations nvgpu_pmu_cmd_post return value was not used in some call sites in pmu perfmon. data structures were forward declared where not reqd are removed and header included where needed. JIRA NVGPU-1971 Change-Id: I8714ed138d1c0b897540b624ae73c70c0a0318e0 Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/2093491 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Adeel Raza GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/acr/acr_priv.h | 1 - .../common/pmu/clk/clk_freq_controller.h | 2 +- .../nvgpu/common/pmu/perfmon/pmu_perfmon.c | 19 ++++++++++++++++--- drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h | 2 -- .../pmu/super_surface/super_surface_priv.h | 1 - drivers/gpu/nvgpu/include/nvgpu/acr.h | 1 - drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h | 1 - .../gpu/nvgpu/include/nvgpu/boardobjgrpmask.h | 3 --- drivers/gpu/nvgpu/include/nvgpu/nvlink.h | 1 - .../nvgpu/include/nvgpu/pmu/clk/clk_domain.h | 1 - .../gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h | 5 ++--- .../nvgpu/pmu/clk/clk_freq_controller.h | 2 +- .../include/nvgpu/pmu/clk/clk_freq_domain.h | 2 +- .../include/nvgpu/pmu/clk/clk_vf_point.h | 3 +-- .../gpu/nvgpu/include/nvgpu/pmu/clk/clk_vin.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h | 1 - drivers/gpu/nvgpu/include/nvgpu/pmu/msg.h | 1 - 17 files changed, 23 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/nvgpu/common/acr/acr_priv.h b/drivers/gpu/nvgpu/common/acr/acr_priv.h index 4cbb78a4e..4c58b0ef2 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_priv.h +++ b/drivers/gpu/nvgpu/common/acr/acr_priv.h @@ -27,7 +27,6 @@ #include "acr_blob_construct_v0.h" #include "acr_blob_construct_v1.h" -struct nvgpu_firmware; struct gk20a; struct nvgpu_acr; struct wpr_carveout_info; diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.h index 5371cee0c..86fad6a92 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.h +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.h @@ -23,7 +23,7 @@ #ifndef NVGPU_CLK_FREQ_CONTROLLER_H #define NVGPU_CLK_FREQ_CONTROLLER_H -struct boardobj; +#include #define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL 0xFFU #define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS 0x00U diff --git a/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon.c index cae7c381d..caa8ca3b7 100644 --- a/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon.c +++ b/drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon.c @@ -197,8 +197,12 @@ int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu) } nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_INIT"); - nvgpu_pmu_cmd_post(g, &cmd, &payload, PMU_COMMAND_QUEUE_LPQ, + status = nvgpu_pmu_cmd_post(g, &cmd, &payload, PMU_COMMAND_QUEUE_LPQ, NULL, NULL); + if (status != 0) { + nvgpu_err(g, "failed cmd post PMU_PERFMON_CMD_ID_INIT"); + return status; + } return 0; } @@ -256,8 +260,12 @@ int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu) } nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_START"); - nvgpu_pmu_cmd_post(g, &cmd, &payload, PMU_COMMAND_QUEUE_LPQ, + status = nvgpu_pmu_cmd_post(g, &cmd, &payload, PMU_COMMAND_QUEUE_LPQ, NULL, NULL); + if (status != 0) { + nvgpu_err(g, "failed cmd post PMU_PERFMON_CMD_ID_START"); + return status; + } return 0; } @@ -267,6 +275,7 @@ int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu) struct gk20a *g = pmu->g; struct pmu_cmd cmd; u64 tmp_size; + int status; if (!nvgpu_is_enabled(g, NVGPU_PMU_PERFMON)) { return 0; @@ -285,8 +294,12 @@ int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu) cmd.cmd.perfmon.stop.cmd_type = PMU_PERFMON_CMD_ID_STOP; nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_STOP"); - nvgpu_pmu_cmd_post(g, &cmd, NULL, PMU_COMMAND_QUEUE_LPQ, + status = nvgpu_pmu_cmd_post(g, &cmd, NULL, PMU_COMMAND_QUEUE_LPQ, NULL, NULL); + if (status != 0) { + nvgpu_err(g, "failed cmd post PMU_PERFMON_CMD_ID_STOP"); + return status; + } return 0; } diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h index 9f6df5666..26fb04ad6 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h @@ -30,8 +30,6 @@ #include #include -struct nvgpu_firmware; - #define ZBC_MASK(i) U16(~(~(0U) << ((i)+1U)) & 0xfffeU) bool gk20a_pmu_is_interrupted(struct nvgpu_pmu *pmu); diff --git a/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h b/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h index 2ebf22e8a..68b3a4635 100644 --- a/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h +++ b/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h @@ -32,7 +32,6 @@ #include struct nvgpu_mem; -struct nv_pmu_super_surface_member_descriptor; /* PMU super surface */ /* 1MB Bytes for SUPER_SURFACE_SIZE */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr.h b/drivers/gpu/nvgpu/include/nvgpu/acr.h index 4965a002a..d0bb01e7e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/acr.h @@ -27,7 +27,6 @@ struct gk20a; struct nvgpu_falcon; struct nvgpu_firmware; struct nvgpu_acr; -struct nv_pmu_rpc_header; int nvgpu_acr_init(struct gk20a *g, struct nvgpu_acr **acr); int nvgpu_acr_alloc_blob_prerequisite(struct gk20a *g, struct nvgpu_acr *acr, diff --git a/drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h b/drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h index 5582774c1..8aba9bde2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h +++ b/drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h @@ -26,7 +26,6 @@ struct boardobjgrp; struct gk20a; struct nvgpu_list_node; -struct pmu_surface; /* ------------------------ Includes ----------------------------------------*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h b/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h index b28e5f8cb..8cedeac3c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h +++ b/drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h @@ -26,9 +26,6 @@ #include #include -struct ctrl_boardobjgrp_mask; - - /* * Board Object Group Mask super-structure. * Used to unify access to all BOARDOBJGRPMASK_E** child classes diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvlink.h b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h index f7ab6436f..1a4b08231 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvlink.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h @@ -46,7 +46,6 @@ #define DLPL_REG_WR32(g, id, off, v) gk20a_writel(g, (g)->nvlink.links[(id)].dlpl_base + (off), (v)) struct gk20a; -struct nvgpu_firmware; struct nvgpu_nvlink_ioctrl_list { bool valid; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_domain.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_domain.h index 7aef57956..48ff020bd 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_domain.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_domain.h @@ -30,7 +30,6 @@ struct gk20a; struct nvgpu_clk_domain; struct nvgpu_clk_slave_freq; -struct ctrl_perf_change_seq_change_input; struct nvgpu_clk_pmupstate; typedef int nvgpu_clkproglink(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk, diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h index 99037a598..745472e37 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h @@ -26,13 +26,12 @@ #define NVGPU_PMU_CLK_FLL_H #include +#include +#include struct gk20a; struct fll_device; struct boardobjgrp_e32; -struct boardobjgrpmask_e32; -struct nv_pmu_clk_lut_device_desc; -struct nv_pmu_clk_regime_desc; struct nvgpu_avfsfllobjs { struct boardobjgrp_e32 super; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_controller.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_controller.h index 99036ef0c..85b468a8d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_controller.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_controller.h @@ -26,10 +26,10 @@ #define NVGPU_PMU_CLK_FREQ_CONTROLLER_H #include +#include struct gk20a; struct boardobjgrp_e32; -struct boardobjgrpmask_e32; struct nvgpu_clk_freq_controllers { struct boardobjgrp_e32 super; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_domain.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_domain.h index b07e6fe6d..32e3ff55c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_domain.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_domain.h @@ -26,9 +26,9 @@ #define NVGPU_PMU_CLK_FREQ_DOMAIN_H #include +#include struct gk20a; -struct boardobj; struct boardobjgrp_e32; struct nvgpu_clk_freq_domain_grp { diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vf_point.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vf_point.h index a69980025..ccb084ba6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vf_point.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vf_point.h @@ -26,11 +26,10 @@ #define NVGPU_PMU_CLK_VF_POINT_H #include +#include struct gk20a; struct boardobjgrp_e255; -struct ctrl_clk_vf_pair; -struct ctrl_clk_freq_delta; struct nvgpu_clk_vf_points { struct boardobjgrp_e255 super; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vin.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vin.h index 556196e8d..bba4578ba 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vin.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vin.h @@ -26,11 +26,11 @@ #define NVGPU_PMU_CLK_VIN_H #include +#include struct gk20a; struct nvgpu_vin_device; struct nvgpu_clk_pmupstate; -struct boardobj; struct boardobjgrp_e32; typedef u32 vin_device_state_load(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h index 9ce585968..9ef800d1b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h @@ -40,7 +40,6 @@ struct nvgpu_pmu; struct pmu_msg; struct pmu_sequence; struct falcon_payload_alloc; -struct nvgpu_engine_fb_queue; typedef void (*pmu_callback)(struct gk20a *g, struct pmu_msg *msg, void *param, u32 status); diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/msg.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/msg.h index de90b7d47..afd567062 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/msg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/msg.h @@ -45,7 +45,6 @@ struct gk20a; struct nvgpu_pmu; struct nvgpu_allocator; struct pmu_sequences; -struct pmu_queues; struct nvgpu_mem; struct nvgpu_falcon;