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gpu: nvgpu: gv11b: set correct max subctx count

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Reading gr_pri_fe_chip_def_info_r() during
gv11b_init_fifo_setup_hw on RTL platforms is giving
"0xbadf1201" error because fecs part of priv ring
is still in reset. This needs to be fixed after
identifying relevant engine that needs to be
brought out of reset. Until that time, use constant
value from hw definition(whose value is 64):
gr_pri_fe_chip_def_info_max_veid_count_init_v().

Bug 1983643

Change-Id: I66f2b6491c9d444c6f6919e76c72ec33a904bc90
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1568139
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
seshendra Gadagottu
2017-09-26 11:22:01 -07:00
committed by mobile promotions
parent 9825a8ec69
commit 1f6755b287
1 changed files with 1 additions and 2 deletions
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3
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
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@@ -1779,8 +1779,7 @@ int gv11b_init_fifo_setup_hw(struct gk20a *g)
f->t19x.usermode_regs = g->regs + usermode_cfg0_r();
f->t19x.max_subctx_count =
gr_pri_fe_chip_def_info_max_veid_count_v(
gk20a_readl(g, gr_pri_fe_chip_def_info_r()));
gr_pri_fe_chip_def_info_max_veid_count_init_v();
return 0;
}