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gpu: nvgpu: Remove hard coded constants from ACR

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During code inspection use of some hard constants was
found in some parts of the code.
Those constants are replaced by macros

JIRA NVGPU-5030

Change-Id: I09212be40746317440218bc7ada9a578dde7c6ed
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2301596
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya Singhatwaria
2020-02-20 17:30:24 +05:30
committed by Alex Waterman
parent 682966ef4c
commit 1f6dfb54d1
4 changed files with 91 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files

113
drivers/gpu/nvgpu/common/acr/acr_blob_construct.c
View File

@@ -33,6 +33,20 @@
#include "acr_wpr.h" #include "acr_wpr.h"
#include "acr_priv.h" #include "acr_priv.h"
#define APP_IMEM_OFFSET (0)
#define APP_IMEM_ENTRY (0)
#define APP_DMEM_OFFSET (0)
#define APP_RESIDENT_CODE_OFFSET (0)
#define MEMSET_VALUE (0)
#define LSB_HDR_DATA_SIZE (0)
#define BL_START_OFFSET (0)
#if defined(CONFIG_NVGPU_DGPU) || defined(CONFIG_NVGPU_LS_PMU)
#define UCODE_PARAMS (1)
#else
#define UCODE_PARAMS (0)
#endif
#ifdef CONFIG_NVGPU_LS_PMU #ifdef CONFIG_NVGPU_LS_PMU
int nvgpu_acr_lsf_pmu_ucode_details(struct gk20a *g, void *lsf_ucode_img) int nvgpu_acr_lsf_pmu_ucode_details(struct gk20a *g, void *lsf_ucode_img)
{ {
@@ -85,7 +99,8 @@ int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
switch (ver) { switch (ver) {
case NVGPU_GPUID_GV11B: case NVGPU_GPUID_GV11B:
fecs_sig = nvgpu_request_firmware(g, GM20B_FECS_UCODE_SIG, 0); fecs_sig = nvgpu_request_firmware(g, GM20B_FECS_UCODE_SIG,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
break; break;
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
case NVGPU_GPUID_TU104: case NVGPU_GPUID_TU104:
@@ -119,21 +134,27 @@ int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
} }
p_img->desc->bootloader_start_offset = fecs->boot.offset; p_img->desc->bootloader_start_offset = fecs->boot.offset;
p_img->desc->bootloader_size = ALIGN(fecs->boot.size, 256U); p_img->desc->bootloader_size = ALIGN(fecs->boot.size,
LSF_DATA_SIZE_ALIGNMENT);
p_img->desc->bootloader_imem_offset = fecs->boot_imem_offset; p_img->desc->bootloader_imem_offset = fecs->boot_imem_offset;
p_img->desc->bootloader_entry_point = fecs->boot_entry; p_img->desc->bootloader_entry_point = fecs->boot_entry;
tmp_size = nvgpu_safe_add_u32(ALIGN(fecs->boot.size, 256U), tmp_size = nvgpu_safe_add_u32(ALIGN(fecs->boot.size,
ALIGN(fecs->code.size, 256U)); LSF_DATA_SIZE_ALIGNMENT),
ALIGN(fecs->code.size,
LSF_DATA_SIZE_ALIGNMENT));
p_img->desc->image_size = nvgpu_safe_add_u32(tmp_size, p_img->desc->image_size = nvgpu_safe_add_u32(tmp_size,
ALIGN(fecs->data.size, 256U)); ALIGN(fecs->data.size,
p_img->desc->app_size = nvgpu_safe_add_u32(ALIGN(fecs->code.size, 256U), LSF_DATA_SIZE_ALIGNMENT));
ALIGN(fecs->data.size, 256U)); p_img->desc->app_size = nvgpu_safe_add_u32(ALIGN(fecs->code.size,
LSF_DATA_SIZE_ALIGNMENT),
ALIGN(fecs->data.size,
LSF_DATA_SIZE_ALIGNMENT));
p_img->desc->app_start_offset = fecs->code.offset; p_img->desc->app_start_offset = fecs->code.offset;
p_img->desc->app_imem_offset = 0; p_img->desc->app_imem_offset = APP_IMEM_OFFSET;
p_img->desc->app_imem_entry = 0; p_img->desc->app_imem_entry = APP_IMEM_ENTRY;
p_img->desc->app_dmem_offset = 0; p_img->desc->app_dmem_offset = APP_DMEM_OFFSET;
p_img->desc->app_resident_code_offset = 0; p_img->desc->app_resident_code_offset = APP_RESIDENT_CODE_OFFSET;
p_img->desc->app_resident_code_size = fecs->code.size; p_img->desc->app_resident_code_size = fecs->code.size;
p_img->desc->app_resident_data_offset = p_img->desc->app_resident_data_offset =
nvgpu_safe_sub_u32(fecs->data.offset, fecs->code.offset); nvgpu_safe_sub_u32(fecs->data.offset, fecs->code.offset);
@@ -168,13 +189,18 @@ int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
nvgpu_gr_falcon_get_gpccs_ucode_segments(gr_falcon); nvgpu_gr_falcon_get_gpccs_ucode_segments(gr_falcon);
int err; int err;
if ((gpccs == NULL) || (gr_falcon == NULL)) {
return -EINVAL;
}
if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) {
return -ENOENT; return -ENOENT;
} }
switch (ver) { switch (ver) {
case NVGPU_GPUID_GV11B: case NVGPU_GPUID_GV11B:
gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG, 0); gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
break; break;
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
case NVGPU_GPUID_TU104: case NVGPU_GPUID_TU104:
@@ -206,33 +232,44 @@ int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
goto free_lsf_desc; goto free_lsf_desc;
} }
p_img->desc->bootloader_start_offset = 0; p_img->desc->bootloader_start_offset = BL_START_OFFSET;
p_img->desc->bootloader_size = ALIGN(gpccs->boot.size, 256U); p_img->desc->bootloader_size = ALIGN(gpccs->boot.size,
LSF_DATA_SIZE_ALIGNMENT);
p_img->desc->bootloader_imem_offset = gpccs->boot_imem_offset; p_img->desc->bootloader_imem_offset = gpccs->boot_imem_offset;
p_img->desc->bootloader_entry_point = gpccs->boot_entry; p_img->desc->bootloader_entry_point = gpccs->boot_entry;
tmp_size = nvgpu_safe_add_u32(ALIGN(gpccs->boot.size, 256U), tmp_size = nvgpu_safe_add_u32(ALIGN(gpccs->boot.size,
ALIGN(gpccs->code.size, 256U)); LSF_DATA_SIZE_ALIGNMENT),
ALIGN(gpccs->code.size,
LSF_DATA_SIZE_ALIGNMENT));
p_img->desc->image_size = nvgpu_safe_add_u32(tmp_size, p_img->desc->image_size = nvgpu_safe_add_u32(tmp_size,
ALIGN(gpccs->data.size, 256U)); ALIGN(gpccs->data.size,
LSF_DATA_SIZE_ALIGNMENT));
p_img->desc->app_size = p_img->desc->app_size =
nvgpu_safe_add_u32(ALIGN(gpccs->code.size, 256U), nvgpu_safe_add_u32(ALIGN(gpccs->code.size,
ALIGN(gpccs->data.size, 256U)); LSF_DATA_SIZE_ALIGNMENT),
ALIGN(gpccs->data.size,
LSF_DATA_SIZE_ALIGNMENT));
p_img->desc->app_start_offset = p_img->desc->bootloader_size; p_img->desc->app_start_offset = p_img->desc->bootloader_size;
p_img->desc->app_imem_offset = 0; p_img->desc->app_imem_offset = APP_IMEM_OFFSET;
p_img->desc->app_imem_entry = 0; p_img->desc->app_imem_entry = APP_IMEM_ENTRY;
p_img->desc->app_dmem_offset = 0; p_img->desc->app_dmem_offset = APP_DMEM_OFFSET;
p_img->desc->app_resident_code_offset = 0; p_img->desc->app_resident_code_offset = APP_RESIDENT_CODE_OFFSET;
p_img->desc->app_resident_code_size = ALIGN(gpccs->code.size, 256U); p_img->desc->app_resident_code_size = ALIGN(gpccs->code.size,
LSF_DATA_SIZE_ALIGNMENT);
p_img->desc->app_resident_data_offset = p_img->desc->app_resident_data_offset =
nvgpu_safe_sub_u32(ALIGN(gpccs->data.offset, 256U), nvgpu_safe_sub_u32(ALIGN(gpccs->data.offset,
ALIGN(gpccs->code.offset, 256U)); LSF_DATA_SIZE_ALIGNMENT),
p_img->desc->app_resident_data_size = ALIGN(gpccs->data.size, 256U); ALIGN(gpccs->code.offset,
LSF_DATA_SIZE_ALIGNMENT));
p_img->desc->app_resident_data_size = ALIGN(gpccs->data.size,
LSF_DATA_SIZE_ALIGNMENT);
p_img->data = (u32 *) p_img->data = (u32 *)
(void *)((u8 *)nvgpu_gr_falcon_get_surface_desc_cpu_va(gr_falcon) (void *)((u8 *)nvgpu_gr_falcon_get_surface_desc_cpu_va(gr_falcon)
+ gpccs->boot.offset); + gpccs->boot.offset);
p_img->data_size = ALIGN(p_img->desc->image_size, 256U); p_img->data_size = ALIGN(p_img->desc->image_size,
LSF_DATA_SIZE_ALIGNMENT);
p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc; p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc;
nvgpu_acr_dbg(g, "gpccs fw loaded\n"); nvgpu_acr_dbg(g, "gpccs fw loaded\n");
@@ -356,7 +393,7 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
pnode->lsb_header.ucode_size = pnode->ucode_img.data_size; pnode->lsb_header.ucode_size = pnode->ucode_img.data_size;
/* Uses a loader. that is has a desc */ /* Uses a loader. that is has a desc */
pnode->lsb_header.data_size = 0; pnode->lsb_header.data_size = LSB_HDR_DATA_SIZE;
/* /*
* The loader code size is already aligned (padded) such that * The loader code size is already aligned (padded) such that
@@ -386,7 +423,7 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
pnode->lsb_header.bl_imem_off = pnode->lsb_header.bl_imem_off =
pnode->ucode_img.desc->bootloader_imem_offset; pnode->ucode_img.desc->bootloader_imem_offset;
pnode->lsb_header.flags = 0; pnode->lsb_header.flags = NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE;
if (falcon_id == FALCON_ID_PMU) { if (falcon_id == FALCON_ID_PMU) {
data = NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE; data = NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE;
@@ -451,7 +488,7 @@ static int lsfm_discover_ucode_images(struct gk20a *g,
if (nvgpu_test_bit(i, (void *)&acr->lsf_enable_mask) && if (nvgpu_test_bit(i, (void *)&acr->lsf_enable_mask) &&
(acr->lsf[i].get_lsf_ucode_details != NULL)) { (acr->lsf[i].get_lsf_ucode_details != NULL)) {
(void) memset(&ucode_img, 0, sizeof(ucode_img)); (void) memset(&ucode_img, MEMSET_VALUE, sizeof(ucode_img));
err = acr->lsf[i].get_lsf_ucode_details(g, err = acr->lsf[i].get_lsf_ucode_details(g,
(void *)&ucode_img); (void *)&ucode_img);
if (err != 0) { if (err != 0) {
@@ -697,7 +734,7 @@ static int lsfm_populate_flcn_bl_dmem_desc(struct gk20a *g,
addr_code, addr_data, desc->bootloader_start_offset); addr_code, addr_data, desc->bootloader_start_offset);
/* Populate the LOADER_CONFIG state */ /* Populate the LOADER_CONFIG state */
(void) memset((void *) ldr_cfg, 0, (void) memset((void *) ldr_cfg, MEMSET_VALUE,
sizeof(struct flcn_bl_dmem_desc)); sizeof(struct flcn_bl_dmem_desc));
ldr_cfg->ctx_dma = g->acr->lsf[falconid].falcon_dma_idx; ldr_cfg->ctx_dma = g->acr->lsf[falconid].falcon_dma_idx;
@@ -708,13 +745,19 @@ static int lsfm_populate_flcn_bl_dmem_desc(struct gk20a *g,
ldr_cfg->data_size = desc->app_resident_data_size; ldr_cfg->data_size = desc->app_resident_data_size;
ldr_cfg->code_entry_point = desc->app_imem_entry; ldr_cfg->code_entry_point = desc->app_imem_entry;
#if defined(CONFIG_NVGPU_DGPU) || defined(CONFIG_NVGPU_LS_PMU)
/* Update the argc/argv members*/ /* Update the argc/argv members*/
ldr_cfg->argc = 1; ldr_cfg->argc = UCODE_PARAMS;
if (g->acr->lsf[falconid].get_cmd_line_args_offset != NULL) { if (g->acr->lsf[falconid].get_cmd_line_args_offset != NULL) {
g->acr->lsf[falconid].get_cmd_line_args_offset(g, g->acr->lsf[falconid].get_cmd_line_args_offset(g,
&ldr_cfg->argv); &ldr_cfg->argv);
} }
#else
/* Update the argc/argv members*/
ldr_cfg->argc = UCODE_PARAMS;
#endif
*p_bl_gen_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc); *p_bl_gen_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc);
return 0; return 0;
} }
@@ -775,7 +818,7 @@ static int lsfm_init_wpr_contents(struct gk20a *g,
/* The WPR array is at the base of the WPR */ /* The WPR array is at the base of the WPR */
pnode = plsfm->ucode_img_list; pnode = plsfm->ucode_img_list;
(void) memset(&last_wpr_hdr, 0, sizeof(struct lsf_wpr_header)); (void) memset(&last_wpr_hdr, MEMSET_VALUE, sizeof(struct lsf_wpr_header));
i = 0; i = 0;
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
@@ -930,7 +973,7 @@ int nvgpu_acr_prepare_ucode_blob(struct gk20a *g)
plsfm = &lsfm_l; plsfm = &lsfm_l;
(void) memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr)); (void) memset((void *)plsfm, MEMSET_VALUE, sizeof(struct ls_flcn_mgr));
err = nvgpu_gr_falcon_init_ctxsw_ucode(g, gr_falcon); err = nvgpu_gr_falcon_init_ctxsw_ucode(g, gr_falcon);
if (err != 0) { if (err != 0) {
nvgpu_err(g, "gr_falcon_init_ctxsw_ucode failed err=%d", err); nvgpu_err(g, "gr_falcon_init_ctxsw_ucode failed err=%d", err);

4
drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -51,7 +51,7 @@
#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0U #define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0U
#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE BIT32(2) #define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE BIT32(2)
#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE BIT32(3) #define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE BIT32(3)
#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0U #define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE (0U)
/* /*
* Image Status Defines * Image Status Defines

14
drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.c
View File

@@ -35,6 +35,9 @@
#include "acr_bootstrap.h" #include "acr_bootstrap.h"
#include "acr_sw_gv11b.h" #include "acr_sw_gv11b.h"
#define RECOVERY_UCODE_BLOB_SIZE (0U)
#define WPR_OFFSET (0U)
static int gv11b_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr) static int gv11b_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr)
{ {
int err = 0; int err = 0;
@@ -60,10 +63,13 @@ static void gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
u32 *acr_ucode_data = NULL; u32 *acr_ucode_data = NULL;
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
#ifdef CONFIG_NVGPU_NON_FUSA
if (is_recovery) { if (is_recovery) {
acr_desc->acr_dmem_desc->nonwpr_ucode_blob_size = 0U; acr_desc->acr_dmem_desc->nonwpr_ucode_blob_size =
} else { RECOVERY_UCODE_BLOB_SIZE;
} else
#endif
{
acr_fw_bin_hdr = (struct bin_hdr *)(void *)acr_fw->data; acr_fw_bin_hdr = (struct bin_hdr *)(void *)acr_fw->data;
acr_fw_hdr = (struct acr_fw_header *)(void *) acr_fw_hdr = (struct acr_fw_header *)(void *)
(acr_fw->data + acr_fw_bin_hdr->header_offset); (acr_fw->data + acr_fw_bin_hdr->header_offset);
@@ -85,7 +91,7 @@ static void gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
acr_dmem_desc->nonwpr_ucode_blob_size = acr_dmem_desc->nonwpr_ucode_blob_size =
(u32)g->acr->ucode_blob.size; (u32)g->acr->ucode_blob.size;
acr_dmem_desc->regions.no_regions = 1U; acr_dmem_desc->regions.no_regions = 1U;
acr_dmem_desc->wpr_offset = 0U; acr_dmem_desc->wpr_offset = WPR_OFFSET;
} }
} }

2
drivers/gpu/nvgpu/common/acr/nvgpu_acr_interface.h
View File

@@ -263,7 +263,7 @@ struct lsf_ucode_desc {
#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE BIT32(2) #define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE BIT32(2)
/** Use priv loading method instead of bootloader/DMAs */ /** Use priv loading method instead of bootloader/DMAs */
#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE BIT32(3) #define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE BIT32(3)
#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0U #define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE (0U)
struct lsf_lsb_header { struct lsf_lsb_header {
/** Code/data signature details of each LS falcon */ /** Code/data signature details of each LS falcon */
struct lsf_ucode_desc signature; struct lsf_ucode_desc signature;