gpu: nvgpu: Fix CERT INT31-C errors in hal.gr.init

Fix CERT INT31-C errors in hal.gr.init unit.
cert-violation: Casting "array_size" from "unsigned long" to "int"
without checking its value may result in lost or misinterpreted data.

Use nvgpu_safe_cast_u64_to_u32 macro to covert size_t to u32

Jira NVGPU-3411

Change-Id: Ib160e43af683d5ca6a1cc86c4b9ee3322ddc971d
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119847
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/gr/gr.c

@@ -285,7 +285,7 @@ static int gr_init_access_map(struct gk20a *g, struct nvgpu_gr *gr)
 		DIV_ROUND_UP(NVGPU_GR_GLOBAL_CTX_PRIV_ACCESS_MAP_SIZE,
 			     PAGE_SIZE);
 	u32 *whitelist = NULL;
-	int w, num_entries = 0;
+	u32 w, num_entries = 0U;
 
 	mem = nvgpu_gr_global_ctx_buffer_get_mem(gr->global_ctx_buffer,
 			NVGPU_GR_GLOBAL_CTX_PRIV_ACCESS_MAP);
@@ -297,7 +297,7 @@ static int gr_init_access_map(struct gk20a *g, struct nvgpu_gr *gr)
 
 	g->ops.gr.init.get_access_map(g, &whitelist, &num_entries);
 
-	for (w = 0; w < num_entries; w++) {
+	for (w = 0U; w < num_entries; w++) {
 		u32 map_bit, map_byte, map_shift, x;
 		map_bit = whitelist[w] >> 2;
 		map_byte = map_bit >> 3;

drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c

@@ -24,6 +24,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/log.h>
 #include <nvgpu/bug.h>
+#include <nvgpu/safe_ops.h>
 #include <nvgpu/timers.h>
 #include <nvgpu/enabled.h>
 #include <nvgpu/engines.h>
@@ -130,7 +131,7 @@ void gm20b_gr_init_fifo_access(struct gk20a *g, bool enable)
 }
 
 void gm20b_gr_init_get_access_map(struct gk20a *g,
-				   u32 **whitelist, int *num_entries)
+				   u32 **whitelist, u32 *num_entries)
 {
 	static u32 wl_addr_gm20b[] = {
 		/* this list must be sorted (low to high) */
@@ -169,7 +170,7 @@ void gm20b_gr_init_get_access_map(struct gk20a *g,
 
 	*whitelist = wl_addr_gm20b;
 	array_size = ARRAY_SIZE(wl_addr_gm20b);
-	*num_entries = (int)array_size;
+	*num_entries = nvgpu_safe_cast_u64_to_u32(array_size);
 }
 
 void gm20b_gr_init_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid,

drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h

@@ -41,7 +41,7 @@ void gm20b_gr_init_pes_vsc_stream(struct gk20a *g);
 void gm20b_gr_init_gpc_mmu(struct gk20a *g);
 void gm20b_gr_init_fifo_access(struct gk20a *g, bool enable);
 void gm20b_gr_init_get_access_map(struct gk20a *g,
-				   u32 **whitelist, int *num_entries);
+				   u32 **whitelist, u32 *num_entries);
 void gm20b_gr_init_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid,
 				   struct nvgpu_gr_config *gr_config);
 u32 gm20b_gr_init_get_sm_id_size(void);

drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c

@@ -24,6 +24,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/log.h>
 #include <nvgpu/bug.h>
+#include <nvgpu/safe_ops.h>
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/gr/config.h>
 #include <nvgpu/gr/gr.h>
@@ -37,7 +38,7 @@
 #define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000U
 
 void gp10b_gr_init_get_access_map(struct gk20a *g,
-				   u32 **whitelist, int *num_entries)
+				   u32 **whitelist, u32 *num_entries)
 {
 	static u32 wl_addr_gp10b[] = {
 		/* this list must be sorted (low to high) */
@@ -76,7 +77,7 @@ void gp10b_gr_init_get_access_map(struct gk20a *g,
 
 	*whitelist = wl_addr_gp10b;
 	array_size = ARRAY_SIZE(wl_addr_gp10b);
-	*num_entries = (int)array_size;
+	*num_entries = nvgpu_safe_cast_u64_to_u32(array_size);
 }
 
 u32 gp10b_gr_init_get_sm_id_size(void)

drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.h

@@ -30,7 +30,7 @@ struct nvgpu_gr_ctx;
 struct nvgpu_gr_config;
 
 void gp10b_gr_init_get_access_map(struct gk20a *g,
-				   u32 **whitelist, int *num_entries);
+				   u32 **whitelist, u32 *num_entries);
 u32 gp10b_gr_init_get_sm_id_size(void);
 int gp10b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id,
 			       struct nvgpu_gr_config *gr_config);

drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c

@@ -25,6 +25,7 @@
 #include <nvgpu/soc.h>
 #include <nvgpu/log.h>
 #include <nvgpu/bug.h>
+#include <nvgpu/safe_ops.h>
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/ltc.h>
 #include <nvgpu/netlist.h>
@@ -326,7 +327,7 @@ void gv11b_gr_init_gpc_mmu(struct gk20a *g)
 }
 
 void gv11b_gr_init_get_access_map(struct gk20a *g,
-				   u32 **whitelist, int *num_entries)
+				   u32 **whitelist, u32 *num_entries)
 {
 	static u32 wl_addr_gv11b[] = {
 		/* this list must be sorted (low to high) */
@@ -365,7 +366,7 @@ void gv11b_gr_init_get_access_map(struct gk20a *g,
 
 	*whitelist = wl_addr_gv11b;
 	array_size = ARRAY_SIZE(wl_addr_gv11b);
-	*num_entries = (int)array_size;
+	*num_entries = nvgpu_safe_cast_u64_to_u32(array_size);
 }
 
 void gv11b_gr_init_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid,

drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h

@@ -36,7 +36,7 @@ void gv11b_gr_init_ecc_scrub_reg(struct gk20a *g,
 				 struct nvgpu_gr_config *gr_config);
 void gv11b_gr_init_gpc_mmu(struct gk20a *g);
 void gv11b_gr_init_get_access_map(struct gk20a *g,
-				   u32 **whitelist, int *num_entries);
+				   u32 **whitelist, u32 *num_entries);
 void gv11b_gr_init_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid,
 				   struct nvgpu_gr_config *gr_config);
 int gv11b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id,

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -683,7 +683,7 @@ struct gpu_ops {
 			void (*gpc_mmu)(struct gk20a *g);
 			void (*fifo_access)(struct gk20a *g, bool enable);
 			void (*get_access_map)(struct gk20a *g,
-				      u32 **whitelist, int *num_entries);
+				      u32 **whitelist, u32 *num_entries);
 			u32 (*get_sm_id_size)(void);
 			int (*sm_id_config)(struct gk20a *g, u32 *tpc_sm_id,
 					    struct nvgpu_gr_config *gr_config);