gpu: nvgpu: Add DT support for TPC_PG_POWERGATE

Added support for TPC_PG_POWERGATE during probe for nvgpu via DT.
A new DT binding GV11B_FUSE_OPT_TPC_DISABLE is supported by nvgpu
driver that checks for valid masks and updates the global tpc_pg_mask
flag.

Bug 200518434

Change-Id: Ia65ae518b48e36d28de5e9375bc994232f6a9438
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117783
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/os/linux/module.c

@@ -32,6 +32,7 @@
 #include <uapi/linux/nvgpu.h>
 #include <dt-bindings/soc/gm20b-fuse.h>
 #include <dt-bindings/soc/gp10b-fuse.h>
+#include <dt-bindings/soc/gv11b-fuse.h>
 
 #include <soc/tegra/fuse.h>
 
@@ -1165,6 +1166,7 @@ static inline void set_gk20a(struct platform_device *pdev, struct gk20a *gk20a)
 static int nvgpu_read_fuse_overrides(struct gk20a *g)
 {
 	struct device_node *np = nvgpu_get_node(g);
+	struct gk20a_platform *platform = dev_get_drvdata(dev_from_gk20a(g));
 	u32 *fuses;
 	int count, i;
 
@@ -1191,6 +1193,10 @@ static int nvgpu_read_fuse_overrides(struct gk20a *g)
 		case GP10B_FUSE_OPT_ECC_EN:
 			g->gr.fecs_feature_override_ecc_val = value;
 			break;
+		case GV11B_FUSE_OPT_TPC_DISABLE:
+			if (platform->set_tpc_pg_mask != NULL)
+				platform->set_tpc_pg_mask(dev_from_gk20a(g), value);
+			break;
 		default:
 			nvgpu_err(g, "ignore unknown fuse override %08x", fuse);
 			break;

drivers/gpu/nvgpu/os/linux/platform_gk20a.h

@@ -196,6 +196,9 @@ struct gk20a_platform {
 	/* Pre callback is called before frequency change */
 	void (*prescale)(struct device *dev);
 
+	/* Set TPC_PG during probe */
+	void (*set_tpc_pg_mask)(struct device *dev, u32 tpc_mask);
+
 	/* Devfreq governor name. If scaling is enabled, we request
 	 * this governor to be used in scaling */
 	const char *devfreq_governor;

drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c

@@ -218,6 +218,28 @@ static int gv11b_tegra_suspend(struct device *dev)
 	return 0;
 }
 
+static bool is_tpc_mask_valid(struct gk20a_platform *platform, u32 tpc_mask)
+{
+	u32 i;
+	bool valid = false;
+
+	for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) {
+		if (tpc_mask == platform->valid_tpc_mask[i])
+			valid = true;
+	}
+	return valid;
+}
+
+static void gv11b_tegra_set_tpc_pg_mask(struct device *dev, u32 tpc_mask)
+{
+	struct gk20a_platform *platform = gk20a_get_platform(dev);
+	struct gk20a *g = get_gk20a(dev);
+
+	if (is_tpc_mask_valid(platform, tpc_mask)) {
+		g->tpc_pg_mask = tpc_mask;
+	}
+}
+
 struct gk20a_platform gv11b_tegra_platform = {
 	.has_syncpoints = true,
 
@@ -237,6 +259,8 @@ struct gk20a_platform gv11b_tegra_platform = {
 	.valid_tpc_mask[1]      = 0x1,
 	.valid_tpc_mask[2]      = 0x5,
 
+	.set_tpc_pg_mask        = gv11b_tegra_set_tpc_pg_mask,
+
 	.can_slcg               = true,
 	.can_blcg               = true,
 	.can_elcg               = true,