nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: gv11b: reading max veid number

Browse Source 
To get maximum number of subctx, sw should read
NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT instead of
LITTER_NUM_SUBCTX.

JIRA GV11B-72

Change-Id: I4d675ba49d8a600da77e7b60da449d9e5ba48971
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1309591
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
seshendra Gadagottu
2017-02-22 10:04:31 -08:00
committed by mobile promotions
parent 53e718a739
commit 207e2ac7d1
5 changed files with 17 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -1657,8 +1657,10 @@ static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index)
struct av_list_gk20a *sw_veid_bundle_init =
&g->gr.ctx_vars.sw_veid_bundle_init;
u32 j;
u32 num_subctx = nvgpu_get_litter_value(g, GPU_LIT_NUM_SUBCTX);
u32 err = 0;
u32 data = gk20a_readl(g, gr_pri_fe_chip_def_info_r());
u32 num_subctx, err = 0;
num_subctx = gr_pri_fe_chip_def_info_max_veid_count_v(data);
for (j = 0; j < num_subctx; j++) {

3
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -35,9 +35,6 @@ enum {
VOLTA_DMA_COPY_A = 0xC3B5,
};
/* use magic number 99 for subctx litter value */
#define GPU_LIT_NUM_SUBCTX 99
#define NVC397_SET_SHADER_EXCEPTIONS 0x1528
#define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280
#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc

3
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -167,9 +167,6 @@ static int gv11b_get_litter_value(struct gk20a *g, int value)
case GPU_LIT_FBPA_STRIDE:
ret = proj_fbpa_stride_v();
break;
case GPU_LIT_NUM_SUBCTX:
ret = proj_litter_num_subctx_v();
break;
default:
break;
}

12
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
View File

@@ -462,6 +462,18 @@ static inline u32 gr_pri_fe_go_idle_info_r(void)
{
return 0x00404194;
}
static inline u32 gr_pri_fe_chip_def_info_r(void)
{
return 0x00404030;
}
static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r)
{
return (r >> 0) & 0xfff;
}
static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void)
{
return 0x00000040;
}
static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
{
return 0x00504238;

6
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -114,10 +114,6 @@ static inline u32 proj_host_num_pbdma_v(void)
{
return 0x00000003;
}
static inline u32 proj_litter_num_subctx_v(void)
{
return 0x00000040;
}
static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
{
return 0x00000004;