From 20b15e6f40edfb892a9927f92d7e6ee35823a770 Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Wed, 19 Dec 2018 12:45:41 +0530 Subject: [PATCH] gpu: nvgpu: move sema specific cmdbuf methods to common/sync/ sema cmdbuf specific functions are only for the sync functionality of nvgpu and do not belong to fifo. construct files sema_cmdbuf_gk20a.h and sema_cmdbuf_gk20a.c under common/sync to contain the syncpt specific cmdbuf functions for arch gk20a. Jira NVGPU-1308 Change-Id: Iebeebe7a3de627f2de08d4ced74bb1aabf1eb53c Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/1975922 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/Makefile.sources | 1 + .../gpu/nvgpu/common/sync/sema_cmdbuf_gk20a.c | 83 +++++++++++++++++++ .../gpu/nvgpu/common/sync/sema_cmdbuf_gk20a.h | 37 +++++++++ drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 54 ------------ drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 6 -- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 7 +- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 7 +- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 7 +- 9 files changed, 134 insertions(+), 69 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gk20a.c create mode 100644 drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gk20a.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 12e69afcd..289fdc15f 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -60,6 +60,7 @@ nvgpu-y += common/bus/bus_gk20a.o \ common/mc/mc_tu104.o \ common/sync/channel_sync.o \ common/sync/channel_sync_semaphore.o \ + common/sync/sema_cmdbuf_gk20a.o \ common/boardobj/boardobj.o \ common/boardobj/boardobjgrp.o \ common/boardobj/boardobjgrpmask.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 4e625f501..1362ce0d0 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -162,6 +162,7 @@ srcs += common/sim.c \ common/sync/channel_sync_semaphore.c \ common/sync/syncpt_cmdbuf_gk20a.c \ common/sync/syncpt_cmdbuf_gv11b.c \ + common/sync/sema_cmdbuf_gk20a.c \ common/clock_gating/gm20b_gating_reglist.c \ common/clock_gating/gp10b_gating_reglist.c \ common/clock_gating/gv11b_gating_reglist.c \ diff --git a/drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gk20a.c b/drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gk20a.c new file mode 100644 index 000000000..817dee64b --- /dev/null +++ b/drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gk20a.c @@ -0,0 +1,83 @@ +/* + * GK20A sema cmdbuf + * + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. +* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +#include "sema_cmdbuf_gk20a.h" + +u32 gk20a_get_sema_wait_cmd_size(void) +{ + return 8U; +} + +u32 gk20a_get_sema_incr_cmd_size(void) +{ + return 10U; +} + +void gk20a_add_sema_cmd(struct gk20a *g, struct nvgpu_semaphore *s, + u64 sema_va, struct priv_cmd_entry *cmd, + u32 off, bool acquire, bool wfi) +{ + nvgpu_log_fn(g, " "); + + /* semaphore_a */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004U); + /* offset_upper */ + nvgpu_mem_wr32(g, cmd->mem, off++, (u32)(sema_va >> 32) & 0xffU); + /* semaphore_b */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005U); + /* offset */ + nvgpu_mem_wr32(g, cmd->mem, off++, (u32)sema_va & 0xffffffff); + + if (acquire) { + /* semaphore_c */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006U); + /* payload */ + nvgpu_mem_wr32(g, cmd->mem, off++, + nvgpu_semaphore_get_value(s)); + /* semaphore_d */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007U); + /* operation: acq_geq, switch_en */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x4U | BIT32(12)); + } else { + /* semaphore_c */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006U); + /* payload */ + nvgpu_mem_wr32(g, cmd->mem, off++, + nvgpu_semaphore_get_value(s)); + /* semaphore_d */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007U); + /* operation: release, wfi */ + nvgpu_mem_wr32(g, cmd->mem, off++, + 0x2UL | ((wfi ? 0x0UL : 0x1UL) << 20)); + /* non_stall_int */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008U); + /* ignored */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0U); + } +} \ No newline at end of file diff --git a/drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gk20a.h b/drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gk20a.h new file mode 100644 index 000000000..b28b78a09 --- /dev/null +++ b/drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gk20a.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_SYNC_SEMA_CMDBUF_GK20A_H +#define NVGPU_SYNC_SEMA_CMDBUF_GK20A_H + +#include + +struct gk20a; +struct priv_cmd_entry; +struct nvgpu_semaphore; + +u32 gk20a_get_sema_wait_cmd_size(void); +u32 gk20a_get_sema_incr_cmd_size(void); +void gk20a_add_sema_cmd(struct gk20a *g, struct nvgpu_semaphore *s, + u64 sema_va, struct priv_cmd_entry *cmd, + u32 off, bool acquire, bool wfi); + +#endif /* NVGPU_SYNC_SEMA_CMDBUF_GK20A_H */ \ No newline at end of file diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 43285b405..b70b8c1e7 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -3467,60 +3467,6 @@ u32 gk20a_fifo_pbdma_acquire_val(u64 timeout) return val; } -u32 gk20a_fifo_get_sema_wait_cmd_size(void) -{ - return 8; -} - -u32 gk20a_fifo_get_sema_incr_cmd_size(void) -{ - return 10; -} - -void gk20a_fifo_add_sema_cmd(struct gk20a *g, - struct nvgpu_semaphore *s, u64 sema_va, - struct priv_cmd_entry *cmd, - u32 off, bool acquire, bool wfi) -{ - nvgpu_log_fn(g, " "); - - /* semaphore_a */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004U); - /* offset_upper */ - nvgpu_mem_wr32(g, cmd->mem, off++, (u32)(sema_va >> 32) & 0xffU); - /* semaphore_b */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005U); - /* offset */ - nvgpu_mem_wr32(g, cmd->mem, off++, (u32)sema_va & 0xffffffffU); - - if (acquire) { - /* semaphore_c */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006U); - /* payload */ - nvgpu_mem_wr32(g, cmd->mem, off++, - nvgpu_semaphore_get_value(s)); - /* semaphore_d */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007U); - /* operation: acq_geq, switch_en */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x4U | BIT32(12)); - } else { - /* semaphore_c */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006U); - /* payload */ - nvgpu_mem_wr32(g, cmd->mem, off++, - nvgpu_semaphore_get_value(s)); - /* semaphore_d */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007U); - /* operation: release, wfi */ - nvgpu_mem_wr32(g, cmd->mem, off++, - 0x2UL | ((wfi ? 0x0UL : 0x1UL) << 20)); - /* non_stall_int */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008U); - /* ignored */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0U); - } -} - bool gk20a_fifo_find_pbdma_for_runlist(struct fifo_gk20a *f, u32 runlist_id, u32 *pbdma_id) { diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index b21b349a4..e9607cf74 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -412,12 +412,6 @@ void gk20a_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, void gk20a_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault); void gk20a_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault); void gk20a_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault); -u32 gk20a_fifo_get_sema_wait_cmd_size(void); -u32 gk20a_fifo_get_sema_incr_cmd_size(void); -void gk20a_fifo_add_sema_cmd(struct gk20a *g, - struct nvgpu_semaphore *s, u64 sema_va, - struct priv_cmd_entry *cmd, - u32 off, bool acquire, bool wfi); int gk20a_fifo_init_userd_slabs(struct gk20a *g); void gk20a_fifo_free_userd_slabs(struct gk20a *g); int gk20a_fifo_init_userd(struct gk20a *g, struct channel_gk20a *c); diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index f50e10550..6a637e1d9 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -55,6 +55,7 @@ #include "common/falcon/falcon_gk20a.h" #include "common/top/top_gm20b.h" #include "common/sync/syncpt_cmdbuf_gk20a.h" +#include "common/sync/sema_cmdbuf_gk20a.h" #include "common/regops/regops_gm20b.h" #include "common/fifo/runlist_gk20a.h" @@ -549,9 +550,9 @@ static const struct gpu_ops gm20b_ops = { .get_syncpt_incr_cmd_size = gk20a_get_syncpt_incr_cmd_size, .get_sync_ro_map = NULL, #endif - .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, - .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, - .add_sema_cmd = gk20a_fifo_add_sema_cmd, + .get_sema_wait_cmd_size = gk20a_get_sema_wait_cmd_size, + .get_sema_incr_cmd_size = gk20a_get_sema_incr_cmd_size, + .add_sema_cmd = gk20a_add_sema_cmd, }, .runlist = { .update_runlist = gk20a_fifo_update_runlist, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 904458ed2..533dad51b 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -66,6 +66,7 @@ #include "common/top/top_gm20b.h" #include "common/top/top_gp10b.h" #include "common/sync/syncpt_cmdbuf_gk20a.h" +#include "common/sync/sema_cmdbuf_gk20a.h" #include "common/regops/regops_gp10b.h" #include "common/fifo/runlist_gk20a.h" @@ -599,9 +600,9 @@ static const struct gpu_ops gp10b_ops = { .get_syncpt_incr_cmd_size = gk20a_get_syncpt_incr_cmd_size, .get_sync_ro_map = NULL, #endif - .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, - .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, - .add_sema_cmd = gk20a_fifo_add_sema_cmd, + .get_sema_wait_cmd_size = gk20a_get_sema_wait_cmd_size, + .get_sema_incr_cmd_size = gk20a_get_sema_incr_cmd_size, + .add_sema_cmd = gk20a_add_sema_cmd, }, .runlist = { .reschedule_runlist = gk20a_fifo_reschedule_runlist, diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index d38cb642c..927b2475b 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -55,6 +55,7 @@ #include "common/falcon/falcon_gk20a.h" #include "common/sync/syncpt_cmdbuf_gk20a.h" +#include "common/sync/sema_cmdbuf_gk20a.h" #include "gp10b/mm_gp10b.h" #include "gp10b/ce_gp10b.h" @@ -420,9 +421,9 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_syncpt_incr_cmd_size = gk20a_get_syncpt_incr_cmd_size, .get_sync_ro_map = NULL, #endif - .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, - .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, - .add_sema_cmd = gk20a_fifo_add_sema_cmd, + .get_sema_wait_cmd_size = gk20a_get_sema_wait_cmd_size, + .get_sema_incr_cmd_size = gk20a_get_sema_incr_cmd_size, + .add_sema_cmd = gk20a_add_sema_cmd, }, .runlist = { .reschedule_runlist = NULL,