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gpu: nvgpu: Selectively disable/enable CFC

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clk_pmu_freq_controller_load used the default mask and affected
all the clock frequency controllers (CFC) which had their bits
set in the mask. We wish to enable/disable the CFCs in isolation
through debugfs. So we add a parameter(bit_idx) to the function
which will help affect only one CFC at a time

JIRA DNVGPU-207

DEPENDS ON: <http://git-master/r/1563302>

Change-Id: I233f52158b4a987bcc058a425380983dbe53fac8
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563303
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2017-07-28 12:20:52 +05:30
committed by mobile promotions
parent 84741589d6
commit 20b746b485
4 changed files with 42 additions and 9 deletions
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3
drivers/gpu/nvgpu/clk/clk_freq_controller.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,7 @@
#ifndef _CLK_FREQ_CONTROLLER_H_
#define _CLK_FREQ_CONTROLLER_H_
#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL 0xFF
#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS 0x00
#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC 0x01
#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR 0x02