diff --git a/drivers/gpu/nvgpu/common/gr/fs_state.c b/drivers/gpu/nvgpu/common/gr/fs_state.c index f43f5aaad..d7c01b429 100644 --- a/drivers/gpu/nvgpu/common/gr/fs_state.c +++ b/drivers/gpu/nvgpu/common/gr/fs_state.c @@ -119,8 +119,10 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config) g->ops.gr.init.pd_tpc_per_gpc(g, config); +#ifdef NVGPU_GRAPHICS /* gr__setup_pd_mapping */ g->ops.gr.init.rop_mapping(g, config); +#endif g->ops.gr.init.pd_skip_table_gpc(g, config); diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c index 1c78a6d8f..8427a20a8 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c @@ -258,6 +258,7 @@ void gm20b_gr_init_tpc_mask(struct gk20a *g, u32 gpc_index, u32 pes_tpc_mask) nvgpu_writel(g, gr_fe_tpc_fs_r(), pes_tpc_mask); } +#ifdef NVGPU_GRAPHICS void gm20b_gr_init_rop_mapping(struct gk20a *g, struct nvgpu_gr_config *gr_config) { @@ -430,6 +431,7 @@ void gm20b_gr_init_rop_mapping(struct gk20a *g, nvgpu_writel(g, gr_rstr2d_gpc_map4_r(), map4); nvgpu_writel(g, gr_rstr2d_gpc_map5_r(), map5); } +#endif int gm20b_gr_init_fs_state(struct gk20a *g) { diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h index 4b206b9ed..d117c4d33 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h @@ -48,8 +48,10 @@ u32 gm20b_gr_init_get_sm_id_size(void); int gm20b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id, struct nvgpu_gr_config *gr_config); void gm20b_gr_init_tpc_mask(struct gk20a *g, u32 gpc_index, u32 pes_tpc_mask); +#ifdef NVGPU_GRAPHICS void gm20b_gr_init_rop_mapping(struct gk20a *g, struct nvgpu_gr_config *gr_config); +#endif int gm20b_gr_init_fs_state(struct gk20a *g); void gm20b_gr_init_pd_tpc_per_gpc(struct gk20a *g, struct nvgpu_gr_config *gr_config); diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c index 1703bf78a..6bd501fd3 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c @@ -473,6 +473,7 @@ void gv11b_gr_init_tpc_mask(struct gk20a *g, u32 gpc_index, u32 pes_tpc_mask) nvgpu_writel(g, gr_fe_tpc_fs_r(gpc_index), pes_tpc_mask); } +#ifdef NVGPU_GRAPHICS void gv11b_gr_init_rop_mapping(struct gk20a *g, struct nvgpu_gr_config *gr_config) { @@ -560,6 +561,7 @@ void gv11b_gr_init_rop_mapping(struct gk20a *g, gr_rstr2d_map_table_cfg_num_entries_f( nvgpu_gr_config_get_tpc_count(gr_config))); } +#endif int gv11b_gr_init_fs_state(struct gk20a *g) { diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h index 3a9af1b6f..5784a2bfb 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.h @@ -42,8 +42,10 @@ void gv11b_gr_init_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid, int gv11b_gr_init_sm_id_config(struct gk20a *g, u32 *tpc_sm_id, struct nvgpu_gr_config *gr_config); void gv11b_gr_init_tpc_mask(struct gk20a *g, u32 gpc_index, u32 pes_tpc_mask); +#ifdef NVGPU_GRAPHICS void gv11b_gr_init_rop_mapping(struct gk20a *g, struct nvgpu_gr_config *gr_config); +#endif int gv11b_gr_init_fs_state(struct gk20a *g); int gv11b_gr_init_preemption_state(struct gk20a *g); void gv11b_gr_init_commit_global_timeslice(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index 926619f97..68f6599be 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -332,7 +332,9 @@ static const struct gpu_ops gm20b_ops = { .sm_id_config = gm20b_gr_init_sm_id_config, .sm_id_numbering = gm20b_gr_init_sm_id_numbering, .tpc_mask = gm20b_gr_init_tpc_mask, +#ifdef NVGPU_GRAPHICS .rop_mapping = gm20b_gr_init_rop_mapping, +#endif .fs_state = gm20b_gr_init_fs_state, .pd_tpc_per_gpc = gm20b_gr_init_pd_tpc_per_gpc, .pd_skip_table_gpc = gm20b_gr_init_pd_skip_table_gpc, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index a0812d193..5028c0c02 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -383,7 +383,9 @@ static const struct gpu_ops gp10b_ops = { .sm_id_config = gp10b_gr_init_sm_id_config, .sm_id_numbering = gm20b_gr_init_sm_id_numbering, .tpc_mask = gm20b_gr_init_tpc_mask, +#ifdef NVGPU_GRAPHICS .rop_mapping = gm20b_gr_init_rop_mapping, +#endif .fs_state = gp10b_gr_init_fs_state, .pd_tpc_per_gpc = gm20b_gr_init_pd_tpc_per_gpc, .pd_skip_table_gpc = gm20b_gr_init_pd_skip_table_gpc, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index d5e8b513e..08856da33 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -464,7 +464,9 @@ static const struct gpu_ops gv11b_ops = { .sm_id_config = gv11b_gr_init_sm_id_config, .sm_id_numbering = gv11b_gr_init_sm_id_numbering, .tpc_mask = gv11b_gr_init_tpc_mask, +#ifdef NVGPU_GRAPHICS .rop_mapping = gv11b_gr_init_rop_mapping, +#endif .fs_state = gv11b_gr_init_fs_state, .pd_tpc_per_gpc = gm20b_gr_init_pd_tpc_per_gpc, .pd_skip_table_gpc = gm20b_gr_init_pd_skip_table_gpc, diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 5414e412b..5f498a7c5 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -504,7 +504,9 @@ static const struct gpu_ops tu104_ops = { .sm_id_config = gv11b_gr_init_sm_id_config, .sm_id_numbering = gv11b_gr_init_sm_id_numbering, .tpc_mask = gv11b_gr_init_tpc_mask, +#ifdef NVGPU_GRAPHICS .rop_mapping = gv11b_gr_init_rop_mapping, +#endif .fs_state = gv11b_gr_init_fs_state, .pd_tpc_per_gpc = gm20b_gr_init_pd_tpc_per_gpc, .pd_skip_table_gpc = gm20b_gr_init_pd_skip_table_gpc, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index cc2869c23..09fdd5cc0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -689,8 +689,10 @@ struct gpu_ops { struct nvgpu_gr_config *gr_config); void (*tpc_mask)(struct gk20a *g, u32 gpc_index, u32 pes_tpc_mask); +#ifdef NVGPU_GRAPHICS void (*rop_mapping)(struct gk20a *g, struct nvgpu_gr_config *gr_config); +#endif /* NVGPU_GRAPHICS */ int (*fs_state)(struct gk20a *g); void (*pd_tpc_per_gpc)(struct gk20a *g, struct nvgpu_gr_config *gr_config);