diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml
index e06482eda..f30177513 100644
--- a/arch/nvgpu-common.yaml
+++ b/arch/nvgpu-common.yaml
@@ -21,8 +21,6 @@ bios:
   gpu: dgpu
   owner: Tejal K
   sources: [ common/vbios/bios.c,
-             common/vbios/bios_sw_gp106.c,
-             common/vbios/bios_sw_gp106.h,
              common/vbios/bios_sw_gv100.c,
              common/vbios/bios_sw_gv100.h,
              common/vbios/bios_sw_tu104.c,
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 30445b45e..33f7153b7 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -527,7 +527,6 @@ nvgpu-y += \
 	common/rbtree.o \
 	common/vbios/bios.o \
 	common/vbios/nvlink_bios.o \
-	common/vbios/bios_sw_gp106.o \
 	common/vbios/bios_sw_gv100.o \
 	common/vbios/bios_sw_tu104.o \
 	common/falcon/falcon.o \
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
index 012367151..b2b7ea9de 100644
--- a/drivers/gpu/nvgpu/Makefile.sources
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -96,7 +96,6 @@ srcs += common/sim/sim.c \
 	common/ecc.c \
 	common/ce/ce.c \
 	common/vbios/bios.c \
-	common/vbios/bios_sw_gp106.c \
 	common/falcon/falcon.c \
 	common/falcon/falcon_sw_gk20a.c \
 	common/falcon/falcon_sw_gp106.c \
diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c
index 803c1b36d..6e6e82c06 100644
--- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c
+++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c
@@ -132,6 +132,11 @@ int gk20a_prepare_poweroff(struct gk20a *g)
 
 	nvgpu_ce_suspend(g);
 
+#ifdef NVGPU_DGPU_SUPPORT
+	/* deinit the bios */
+	nvgpu_bios_sw_deinit(g, g->bios);
+#endif
+
 	/* Disable GPCPLL */
 	if (g->ops.clk.suspend_clk_support != NULL) {
 		g->ops.clk.suspend_clk_support(g);
@@ -238,13 +243,11 @@ int gk20a_finalize_poweron(struct gk20a *g)
 		}
 	}
 
-	if (g->ops.bios.init != NULL) {
-		err = g->ops.bios.init(g);
-	}
+	err = nvgpu_bios_sw_init(g, &g->bios);
 	if (err != 0) {
+		nvgpu_err(g, "BIOS SW init failed %d", err);
 		goto done;
 	}
-
 	g->ops.bus.init_hw(g);
 
 	if (g->ops.clk.disable_slowboot != NULL) {
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c
index 9d16f3364..1b1c48562 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c
@@ -593,7 +593,8 @@ static int devinit_get_clocks_table(struct gk20a *g,
 	nvgpu_log_info(g, " ");
 
 	clocks_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.clock_token, CLOCKS_TABLE);
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_CLOCK_TOKEN),
+							CLOCKS_TABLE);
 	if (clocks_table_ptr == NULL) {
 		status = -EINVAL;
 		goto done;
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
index 3060b71f8..5432a942f 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c
@@ -275,7 +275,8 @@ static int devinit_get_fll_device_table(struct gk20a *g,
 	nvgpu_log_info(g, " ");
 
 	fll_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			  g->bios.clock_token, FLL_TABLE);
+			  nvgpu_bios_get_bit_token(g, NVGPU_BIOS_CLOCK_TOKEN),
+							FLL_TABLE);
 	if (fll_table_ptr == NULL) {
 		status = -1;
 		goto done;
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c
index 908968dd5..1bff87114 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c
@@ -231,7 +231,7 @@ static int clk_get_freq_controller_table(struct gk20a *g,
 
 	pfreq_controller_table_ptr =
 		(u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.clock_token,
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_CLOCK_TOKEN),
 			FREQUENCY_CONTROLLER_TABLE);
 	if (pfreq_controller_table_ptr == NULL) {
 		status = -EINVAL;
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c
index f503ae960..5a65711c8 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c
@@ -457,7 +457,8 @@ static int devinit_get_clk_prog_table(struct gk20a *g,
 	nvgpu_log_info(g, " ");
 
 	clkprogs_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.clock_token, CLOCK_PROGRAMMING_TABLE);
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_CLOCK_TOKEN),
+						CLOCK_PROGRAMMING_TABLE);
 	if (clkprogs_tbl_ptr == NULL) {
 		return -EINVAL;
 	}
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c
index ff24e99c3..9b2542650 100644
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c
+++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c
@@ -281,7 +281,8 @@ static int devinit_get_vin_device_table(struct gk20a *g,
 	nvgpu_log_info(g, " ");
 
 	vin_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.clock_token, VIN_TABLE);
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_CLOCK_TOKEN),
+						VIN_TABLE);
 	if (vin_table_ptr == NULL) {
 		status = -1;
 		goto done;
diff --git a/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c b/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c
index d6392e5e6..266772777 100644
--- a/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c
+++ b/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c
@@ -30,7 +30,6 @@
 #include <nvgpu/pmu/pmu_pstate.h>
 #include <nvgpu/pmu/pmu_pg.h>
 
-#include "common/vbios/bios_sw_gp106.h"
 #include "lpwr.h"
 
 static int get_lpwr_idx_table(struct gk20a *g)
@@ -44,7 +43,8 @@ static int get_lpwr_idx_table(struct gk20a *g)
 	struct nvgpu_bios_lpwr_idx_table_1x_entry entry = { 0 };
 
 	lpwr_idx_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-		g->bios.perf_token, LOWPOWER_TABLE);
+		nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
+					LOWPOWER_TABLE);
 	if (lpwr_idx_table_ptr == NULL) {
 		return -EINVAL;
 	}
@@ -88,7 +88,8 @@ static int get_lpwr_gr_table(struct gk20a *g)
 	struct nvgpu_bios_lpwr_gr_table_1x_entry entry = { 0 };
 
 	lpwr_gr_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-		g->bios.perf_token, LOWPOWER_GR_TABLE);
+		nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
+						LOWPOWER_GR_TABLE);
 	if (lpwr_gr_table_ptr == NULL) {
 		return -EINVAL;
 	}
@@ -134,7 +135,8 @@ static int get_lpwr_ms_table(struct gk20a *g)
 	struct nvgpu_bios_lpwr_ms_table_1x_entry entry = { 0 };
 
 	lpwr_ms_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-		g->bios.perf_token, LOWPOWER_MS_TABLE);
+		nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
+						LOWPOWER_MS_TABLE);
 	if (lpwr_ms_table_ptr == NULL) {
 		return -EINVAL;
 	}
diff --git a/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c b/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c
index f8ea5ef26..0caadd6ac 100644
--- a/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c
+++ b/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c
@@ -27,7 +27,6 @@
 #include <nvgpu/pmu/cmd.h>
 #include <nvgpu/pmu/pmu_pstate.h>
 
-#include "common/vbios/bios_sw_gp106.h"
 
 static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg,
 	void *param, u32 status)
diff --git a/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c b/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c
index ac29af42b..892c887d1 100644
--- a/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c
+++ b/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c
@@ -227,7 +227,8 @@ int nvgpu_pmu_perf_pstate_sw_setup(struct gk20a *g)
 
 	hdr = (struct vbios_pstate_header_6x *)
 			nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.perf_token, PERFORMANCE_TABLE);
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
+						PERFORMANCE_TABLE);
 
 	if (hdr == NULL) {
 		nvgpu_err(g, "performance table not found");
diff --git a/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c b/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c
index d17f98428..42f239c4d 100644
--- a/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c
+++ b/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c
@@ -168,7 +168,7 @@ static int devinit_get_vfe_equ_table(struct gk20a *g,
 	nvgpu_log_info(g, " ");
 
 	vfeequs_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.perf_token,
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
 			CONTINUOUS_VIRTUAL_BINNING_TABLE);
 
 	if (vfeequs_tbl_ptr == NULL) {
diff --git a/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c b/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c
index d38ec0e4a..a0b3b05d9 100644
--- a/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c
+++ b/drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c
@@ -275,14 +275,16 @@ static int dev_init_get_vfield_info(struct gk20a *g,
 	int status = 0;
 
 	vfieldregtableptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.virt_token, VP_FIELD_REGISTER);
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_VIRT_TOKEN),
+			VP_FIELD_REGISTER);
 	if (vfieldregtableptr == NULL) {
 		status = -EINVAL;
 		goto done;
 	}
 
 	vfieldtableptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.virt_token, VP_FIELD_TABLE);
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_VIRT_TOKEN),
+			VP_FIELD_TABLE);
 	if (vfieldtableptr == NULL) {
 		status = -EINVAL;
 		goto done;
@@ -1079,7 +1081,7 @@ static int devinit_get_vfe_var_table(struct gk20a *g,
 	nvgpu_log_info(g, " ");
 
 	vfevars_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.perf_token,
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
 			CONTINUOUS_VIRTUAL_BINNING_TABLE);
 	if (vfevars_tbl_ptr == NULL) {
 		status = -EINVAL;
diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c
index aec49078e..4af420bf8 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c
@@ -30,8 +30,6 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/pmu/cmd.h>
 
-#include "common/vbios/bios_sw_gp106.h"
-
 #include "pwrdev.h"
 #include "pmgr.h"
 #include "pmgrpmu.h"
diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c
index 972a3404c..55822a47e 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c
@@ -28,7 +28,6 @@
 
 #include "pwrdev.h"
 #include "pmgr.h"
-#include "common/vbios/bios_sw_gp106.h"
 
 static int _pwr_device_pmudata_instget(struct gk20a *g,
 			struct nv_pmu_boardobjgrp *pmuboardobjgrp,
@@ -152,7 +151,8 @@ static int devinit_get_pwr_device_table(struct gk20a *g,
 	nvgpu_log_info(g, " ");
 
 	pwr_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.perf_token, POWER_SENSORS_TABLE);
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
+						POWER_SENSORS_TABLE);
 	if (pwr_device_table_ptr == NULL) {
 		status = -EINVAL;
 		goto done;
diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c
index 53d2dd983..c04ba6288 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c
@@ -28,7 +28,6 @@
 
 #include "pwrdev.h"
 #include "pmgr.h"
-#include "common/vbios/bios_sw_gp106.h"
 
 static int _pwr_channel_pmudata_instget(struct gk20a *g,
 			struct nv_pmu_boardobjgrp *pmuboardobjgrp,
@@ -205,7 +204,8 @@ static int devinit_get_pwr_topology_table(struct gk20a *g,
 	nvgpu_log_info(g, " ");
 
 	pwr_topology_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.perf_token, POWER_TOPOLOGY_TABLE);
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
+						POWER_TOPOLOGY_TABLE);
 	if (pwr_topology_table_ptr == NULL) {
 		status = -EINVAL;
 		goto done;
diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c
index 3817c55b0..c02e08b87 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c
@@ -29,7 +29,6 @@
 
 #include "pwrpolicy.h"
 #include "pmgr.h"
-#include "common/vbios/bios_sw_gp106.h"
 
 #define _pwr_policy_limitarboutputget_helper(p_limit_arb) (p_limit_arb)->output
 #define _pwr_policy_limitdeltaapply(limit, delta) ((u32)max(((s32)limit) + (delta), 0))
@@ -536,7 +535,8 @@ static int devinit_get_pwr_policy_table(struct gk20a *g,
 	nvgpu_log_info(g, " ");
 
 	ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.perf_token, POWER_CAPPING_TABLE);
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
+						POWER_CAPPING_TABLE);
 	if (ptr == NULL) {
 		status = -EINVAL;
 		goto done;
diff --git a/drivers/gpu/nvgpu/common/pmu/therm/thrmchannel.c b/drivers/gpu/nvgpu/common/pmu/therm/thrmchannel.c
index 541f7c4d3..e85cb1e4d 100644
--- a/drivers/gpu/nvgpu/common/pmu/therm/thrmchannel.c
+++ b/drivers/gpu/nvgpu/common/pmu/therm/thrmchannel.c
@@ -144,7 +144,8 @@ static int devinit_get_therm_channel_table(struct gk20a *g,
 	nvgpu_log_info(g, " ");
 
 	therm_channel_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.perf_token, THERMAL_CHANNEL_TABLE);
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
+						THERMAL_CHANNEL_TABLE);
 	if (therm_channel_table_ptr == NULL) {
 		status = -EINVAL;
 		goto done;
diff --git a/drivers/gpu/nvgpu/common/pmu/therm/thrmdev.c b/drivers/gpu/nvgpu/common/pmu/therm/thrmdev.c
index 794e15a35..e2c16c514 100644
--- a/drivers/gpu/nvgpu/common/pmu/therm/thrmdev.c
+++ b/drivers/gpu/nvgpu/common/pmu/therm/thrmdev.c
@@ -244,7 +244,8 @@ static int devinit_get_therm_device_table(struct gk20a *g,
 	nvgpu_log_info(g, " ");
 
 	therm_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.perf_token, THERMAL_DEVICE_TABLE);
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
+			THERMAL_DEVICE_TABLE);
 	if (therm_device_table_ptr == NULL) {
 		status = -EINVAL;
 		goto done;
diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c b/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c
index 825ea308d..6dbf9cb44 100644
--- a/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c
+++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_dev.c
@@ -401,7 +401,8 @@ static int volt_get_volt_devices_table(struct gk20a *g,
 	u8 *entry_offset;
 
 	volt_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.perf_token, VOLTAGE_DEVICE_TABLE);
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
+			VOLTAGE_DEVICE_TABLE);
 	if (volt_device_table_ptr == NULL) {
 		status = -EINVAL;
 		goto done;
diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c b/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c
index def4f40ae..30526bdfc 100644
--- a/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c
+++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_policy.c
@@ -318,7 +318,8 @@ static int volt_get_volt_policy_table(struct gk20a *g,
 
 	voltage_policy_table_ptr =
 		(u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.perf_token, VOLTAGE_POLICY_TABLE);
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
+			VOLTAGE_POLICY_TABLE);
 	if (voltage_policy_table_ptr == NULL) {
 		status = -EINVAL;
 		goto done;
diff --git a/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c b/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c
index 985839775..619de43c3 100644
--- a/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c
+++ b/drivers/gpu/nvgpu/common/pmu/volt/volt_rail.c
@@ -174,7 +174,8 @@ static int volt_get_volt_rail_table(struct gk20a *g,
 	} rail_type_data;
 
 	volt_rail_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			g->bios.perf_token, VOLTAGE_RAIL_TABLE);
+			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_PERF_TOKEN),
+			VOLTAGE_RAIL_TABLE);
 	if (volt_rail_table_ptr == NULL) {
 		status = -EINVAL;
 		goto done;
diff --git a/drivers/gpu/nvgpu/common/vbios/bios.c b/drivers/gpu/nvgpu/common/vbios/bios.c
index 1896a0a16..06a4b6ef7 100644
--- a/drivers/gpu/nvgpu/common/vbios/bios.c
+++ b/drivers/gpu/nvgpu/common/vbios/bios.c
@@ -24,22 +24,205 @@
 #include <nvgpu/io.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/string.h>
+#include <nvgpu/soc.h>
+
+#include "bios_sw_gv100.h"
+#include "bios_sw_tu104.h"
 
 static void nvgpu_bios_parse_bit(struct gk20a *g, u32 offset);
 
+int nvgpu_bios_devinit(struct gk20a *g,
+		 struct nvgpu_bios *bios)
+{
+	if (bios == NULL) {
+		return 0;
+	}
+
+	if (bios->devinit_bios != NULL) {
+		return bios->devinit_bios(g);
+	} else {
+		return 0;
+	}
+}
+
+int nvgpu_bios_preos_wait_for_halt(struct gk20a *g,
+		 struct nvgpu_bios *bios)
+{
+	if (bios == NULL) {
+		return 0;
+	}
+
+	if (bios->preos_wait_for_halt != NULL) {
+		return bios->preos_wait_for_halt(g);
+	} else {
+		return 0;
+	}
+}
+
+bool nvgpu_bios_check_dgpu(struct gk20a *g, u32 ver)
+{
+	bool is_supported;
+
+	switch (ver) {
+
+	case NVGPU_GPUID_GV100:
+	case NVGPU_GPUID_TU104:
+		is_supported = true;
+		break;
+
+	default:
+		is_supported = false;
+		break;
+	}
+
+	return is_supported;
+}
+
+u32  nvgpu_bios_get_vbios_version(struct gk20a *g)
+{
+	u32 ver = g->params.gpu_arch + g->params.gpu_impl;
+	u32 vbios_version;
+
+	switch (ver) {
+
+	case NVGPU_GPUID_GV100:
+	case NVGPU_GPUID_TU104:
+		if (nvgpu_platform_is_silicon(g)) {
+			vbios_version = g->bios->vbios_version;
+		} else {
+			vbios_version = 0;
+		}
+		break;
+
+	default:
+		vbios_version = 0;
+		break;
+	}
+
+	return vbios_version;
+}
+
+u8  nvgpu_bios_get_vbios_oem_version(struct gk20a *g)
+{
+	u32 ver = g->params.gpu_arch + g->params.gpu_impl;
+	u8 vbios_oem_version;
+
+	switch (ver) {
+
+	case NVGPU_GPUID_GV100:
+	case NVGPU_GPUID_TU104:
+		if (nvgpu_platform_is_silicon(g)) {
+			vbios_oem_version = g->bios->vbios_oem_version;
+		} else {
+			vbios_oem_version = 0;
+		}
+		break;
+
+	default:
+		vbios_oem_version = 0;
+		break;
+	}
+
+	return vbios_oem_version;
+}
+
+struct bit_token *nvgpu_bios_get_bit_token(struct gk20a *g, u8 token_id)
+{
+	struct bit_token *token = NULL;
+
+	switch (token_id) {
+	case NVGPU_BIOS_CLOCK_TOKEN:
+		token = g->bios->clock_token;
+		break;
+
+	case NVGPU_BIOS_PERF_TOKEN:
+		token = g->bios->perf_token;
+		break;
+
+	case NVGPU_BIOS_VIRT_TOKEN:
+		token = g->bios->virt_token;
+		break;
+	}
+
+	return token;
+}
+
+int nvgpu_bios_sw_init(struct gk20a *g,
+		struct nvgpu_bios **bios)
+{
+	u32 ver = g->params.gpu_arch + g->params.gpu_impl;
+	int err = 0;
+
+	if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
+		goto done;
+	}
+
+	if (nvgpu_bios_check_dgpu(g, ver) == false) {
+		goto done;
+	}
+
+	if (*bios != NULL) {
+		/* skip alloc/reinit for unrailgate sequence */
+		nvgpu_pmu_dbg(g, "skip bios init for unrailgate sequence");
+		goto done;
+	}
+
+	*bios = (struct nvgpu_bios *)
+		nvgpu_kzalloc(g, sizeof(struct nvgpu_bios));
+	if (*bios == NULL) {
+		err = -ENOMEM;
+		goto done;
+	}
+
+	switch (ver) {
+#ifdef NVGPU_DGPU_SUPPORT
+	case NVGPU_GPUID_GV100:
+		nvgpu_gv100_bios_sw_init(g, *bios);
+		break;
+
+	case NVGPU_GPUID_TU104:
+		nvgpu_tu104_bios_sw_init(g, *bios);
+		break;
+#endif
+	default:
+		nvgpu_kfree(g, *bios);
+		err = 0;
+		break;
+	}
+
+	if ((*bios)->init != NULL) {
+		err = (*bios)->init(g);
+		if (err != 0)
+			nvgpu_falcon_sw_free(g, FALCON_ID_FECS);
+		goto done;
+	}
+
+done:
+	return err;
+}
+
+void nvgpu_bios_sw_deinit(struct gk20a *g, struct nvgpu_bios *bios)
+{
+	if (bios == NULL) {
+		return;
+	} else {
+		nvgpu_kfree(g, bios);
+	}
+}
+
 static u16 nvgpu_bios_rdu16(struct gk20a *g, u32 offset)
 {
-	u16 val = (U16(g->bios.data[offset+1U]) << U16(8)) +
-		U16(g->bios.data[offset]);
+	u16 val = (U16(g->bios->data[offset+1U]) << U16(8)) +
+		U16(g->bios->data[offset]);
 	return val;
 }
 
 static u32 nvgpu_bios_rdu32(struct gk20a *g, u32 offset)
 {
-	u32 val = (U32(g->bios.data[offset+3U]) << U32(24)) +
-		  (U32(g->bios.data[offset+2U]) << U32(16)) +
-		  (U32(g->bios.data[offset+1U]) << U32(8)) +
-		  U32(g->bios.data[offset]);
+	u32 val = (U32(g->bios->data[offset+3U]) << U32(24)) +
+		  (U32(g->bios->data[offset+2U]) << U32(16)) +
+		  (U32(g->bios->data[offset+1U]) << U32(8)) +
+		  U32(g->bios->data[offset]);
 	return val;
 }
 
@@ -55,7 +238,7 @@ int nvgpu_bios_parse_rom(struct gk20a *g)
 		struct pci_data_struct pci_data;
 		struct pci_ext_data_struct pci_ext_data;
 
-		nvgpu_memcpy((u8 *)&pci_rom, (u8 *)(g->bios.data + offset),
+		nvgpu_memcpy((u8 *)&pci_rom, (u8 *)(g->bios->data + offset),
 				sizeof(struct pci_exp_rom));
 		nvgpu_log_fn(g, "pci rom sig %04x ptr %04x block %x",
 				pci_rom.sig, pci_rom.pci_data_struct_ptr,
@@ -67,7 +250,7 @@ int nvgpu_bios_parse_rom(struct gk20a *g)
 			return -EINVAL;
 		}
 
-		nvgpu_memcpy((u8 *)&pci_data, (u8 *)(g->bios.data + offset +
+		nvgpu_memcpy((u8 *)&pci_data, (u8 *)(g->bios->data + offset +
 				pci_rom.pci_data_struct_ptr),
 				sizeof(struct pci_data_struct));
 		nvgpu_log_fn(g, "pci data sig %08x len %d image len %x type %x last %d max %08x",
@@ -79,10 +262,10 @@ int nvgpu_bios_parse_rom(struct gk20a *g)
 		/* Get Base ROM Size */
 		if (pci_data.code_type ==
 				PCI_DATA_STRUCTURE_CODE_TYPE_VBIOS_BASE) {
-			g->bios.base_rom_size = (u32)pci_data.image_len *
+			g->bios->base_rom_size = (u32)pci_data.image_len *
 						PCI_ROM_IMAGE_BLOCK_SIZE;
 			nvgpu_log_fn(g, "Base ROM Size: %x",
-						g->bios.base_rom_size);
+						g->bios->base_rom_size);
 		}
 
 		/* Get Expansion ROM offset:
@@ -100,7 +283,7 @@ int nvgpu_bios_parse_rom(struct gk20a *g)
 					  pci_rom.pci_data_struct_ptr +
 					  pci_data.pci_data_struct_len +
 					  0xfU) & ~0xfU;
-			nvgpu_memcpy((u8 *)&pci_ext_data, (u8 *)(g->bios.data +
+			nvgpu_memcpy((u8 *)&pci_ext_data, (u8 *)(g->bios->data +
 					ext_offset),
 					sizeof(struct pci_ext_data_struct));
 			nvgpu_log_fn(g, "pci ext data sig %08x rev %x len %x sub_image_len %x priv_last %d flags %x",
@@ -114,7 +297,7 @@ int nvgpu_bios_parse_rom(struct gk20a *g)
 			nvgpu_log_fn(g, "expansion rom offset %x",
 					pci_data.image_len *
 						PCI_ROM_IMAGE_BLOCK_SIZE);
-			g->bios.expansion_rom_offset =
+			g->bios->expansion_rom_offset =
 					(u32)pci_data.image_len *
 						PCI_ROM_IMAGE_BLOCK_SIZE;
 			offset += (u32)pci_ext_data.sub_image_len *
@@ -128,7 +311,7 @@ int nvgpu_bios_parse_rom(struct gk20a *g)
 	}
 
 	nvgpu_log_info(g, "read bios");
-	for (i = 0; i < g->bios.size - 6U; i++) {
+	for (i = 0; i < g->bios->size - 6U; i++) {
 		if (nvgpu_bios_rdu16(g, i) == BIT_HEADER_ID &&
 		    nvgpu_bios_rdu32(g, i+2U) ==  BIT_HEADER_SIGNATURE) {
 			nvgpu_bios_parse_bit(g, i);
@@ -147,33 +330,33 @@ static void nvgpu_bios_parse_biosdata(struct gk20a *g, u32 offset)
 {
 	struct biosdata bios_data;
 
-	nvgpu_memcpy((u8 *)&bios_data, &g->bios.data[offset],
+	nvgpu_memcpy((u8 *)&bios_data, &g->bios->data[offset],
 			sizeof(bios_data));
 	nvgpu_log_fn(g, "bios version %x, oem version %x",
 			bios_data.version,
 			bios_data.oem_version);
 
-	g->bios.vbios_version = bios_data.version;
-	g->bios.vbios_oem_version = bios_data.oem_version;
+	g->bios->vbios_version = bios_data.version;
+	g->bios->vbios_oem_version = bios_data.oem_version;
 }
 
 static void nvgpu_bios_parse_nvinit_ptrs(struct gk20a *g, u32 offset)
 {
 	struct nvinit_ptrs init_ptrs;
 
-	nvgpu_memcpy((u8 *)&init_ptrs, &g->bios.data[offset],
+	nvgpu_memcpy((u8 *)&init_ptrs, &g->bios->data[offset],
 		sizeof(init_ptrs));
 	nvgpu_log_fn(g, "devinit ptr %x size %d", init_ptrs.devinit_tables_ptr,
 			init_ptrs.devinit_tables_size);
 	nvgpu_log_fn(g, "bootscripts ptr %x size %d", init_ptrs.bootscripts_ptr,
 			init_ptrs.bootscripts_size);
 
-	g->bios.devinit_tables = &g->bios.data[init_ptrs.devinit_tables_ptr];
-	g->bios.devinit_tables_size = init_ptrs.devinit_tables_size;
-	g->bios.bootscripts = &g->bios.data[init_ptrs.bootscripts_ptr];
-	g->bios.bootscripts_size = init_ptrs.bootscripts_size;
-	g->bios.condition_table_ptr = init_ptrs.condition_table_ptr;
-	g->bios.nvlink_config_data_offset = init_ptrs.nvlink_config_data_ptr;
+	g->bios->devinit_tables = &g->bios->data[init_ptrs.devinit_tables_ptr];
+	g->bios->devinit_tables_size = init_ptrs.devinit_tables_size;
+	g->bios->bootscripts = &g->bios->data[init_ptrs.bootscripts_ptr];
+	g->bios->bootscripts_size = init_ptrs.bootscripts_size;
+	g->bios->condition_table_ptr = init_ptrs.condition_table_ptr;
+	g->bios->nvlink_config_data_offset = init_ptrs.nvlink_config_data_ptr;
 }
 static void nvgpu_bios_parse_memory_ptrs(struct gk20a *g, u16 offset, u8 version)
 {
@@ -182,14 +365,14 @@ static void nvgpu_bios_parse_memory_ptrs(struct gk20a *g, u16 offset, u8 version
 
 	switch (version) {
 	case MEMORY_PTRS_V1:
-		nvgpu_memcpy((u8 *)&v1, &g->bios.data[offset], sizeof(v1));
-		g->bios.mem_strap_data_count = v1.mem_strap_data_count;
-		g->bios.mem_strap_xlat_tbl_ptr = v1.mem_strap_xlat_tbl_ptr;
+		nvgpu_memcpy((u8 *)&v1, &g->bios->data[offset], sizeof(v1));
+		g->bios->mem_strap_data_count = v1.mem_strap_data_count;
+		g->bios->mem_strap_xlat_tbl_ptr = v1.mem_strap_xlat_tbl_ptr;
 		break;
 	case MEMORY_PTRS_V2:
-		nvgpu_memcpy((u8 *)&v2, &g->bios.data[offset], sizeof(v2));
-		g->bios.mem_strap_data_count = v2.mem_strap_data_count;
-		g->bios.mem_strap_xlat_tbl_ptr = v2.mem_strap_xlat_tbl_ptr;
+		nvgpu_memcpy((u8 *)&v2, &g->bios->data[offset], sizeof(v2));
+		g->bios->mem_strap_data_count = v2.mem_strap_data_count;
+		g->bios->mem_strap_xlat_tbl_ptr = v2.mem_strap_xlat_tbl_ptr;
 		break;
 	default:
 		nvgpu_err(g, "unknown vbios memory table version %x", version);
@@ -203,7 +386,7 @@ static void nvgpu_bios_parse_devinit_appinfo(struct gk20a *g, u32 dmem_offset)
 {
 	struct devinit_engine_interface interface;
 
-	nvgpu_memcpy((u8 *)&interface, &g->bios.devinit.dmem[dmem_offset],
+	nvgpu_memcpy((u8 *)&interface, &g->bios->devinit.dmem[dmem_offset],
 		sizeof(interface));
 	nvgpu_log_fn(g, "devinit version %x tables phys %x script phys %x size %d",
 			interface.version,
@@ -214,8 +397,8 @@ static void nvgpu_bios_parse_devinit_appinfo(struct gk20a *g, u32 dmem_offset)
 	if (interface.version != 1U) {
 		return;
 	}
-	g->bios.devinit_tables_phys_base = interface.tables_phys_base;
-	g->bios.devinit_script_phys_base = interface.script_phys_base;
+	g->bios->devinit_tables_phys_base = interface.tables_phys_base;
+	g->bios->devinit_script_phys_base = interface.script_phys_base;
 }
 
 static int nvgpu_bios_parse_appinfo_table(struct gk20a *g, u32 offset)
@@ -223,7 +406,7 @@ static int nvgpu_bios_parse_appinfo_table(struct gk20a *g, u32 offset)
 	struct application_interface_table_hdr_v1 hdr;
 	u32 i;
 
-	nvgpu_memcpy((u8 *)&hdr, &g->bios.data[offset], sizeof(hdr));
+	nvgpu_memcpy((u8 *)&hdr, &g->bios->data[offset], sizeof(hdr));
 
 	nvgpu_log_fn(g, "appInfoHdr ver %d size %d entrySize %d entryCount %d",
 			hdr.version, hdr.header_size,
@@ -237,7 +420,7 @@ static int nvgpu_bios_parse_appinfo_table(struct gk20a *g, u32 offset)
 	for (i = 0U; i < hdr.entry_count; i++) {
 		struct application_interface_entry_v1 entry;
 
-		nvgpu_memcpy((u8 *)&entry, &g->bios.data[offset],
+		nvgpu_memcpy((u8 *)&entry, &g->bios->data[offset],
 			sizeof(entry));
 
 		nvgpu_log_fn(g, "appInfo id %d dmem_offset %d",
@@ -262,7 +445,7 @@ static int nvgpu_bios_parse_falcon_ucode_desc(struct gk20a *g,
 	u16 desc_size;
 	int ret = 0;
 
-	nvgpu_memcpy((u8 *)&udesc, &g->bios.data[offset], sizeof(udesc));
+	nvgpu_memcpy((u8 *)&udesc, &g->bios->data[offset], sizeof(udesc));
 
 	if (FALCON_UCODE_IS_VERSION_AVAILABLE(udesc)) {
 		version = FALCON_UCODE_GET_VERSION(udesc);
@@ -322,7 +505,7 @@ static int nvgpu_bios_parse_falcon_ucode_desc(struct gk20a *g,
 	}
 
 	ucode->code_entry_point = desc.virtual_entry;
-	ucode->bootloader = &g->bios.data[offset] + desc_size;
+	ucode->bootloader = &g->bios->data[offset] + desc_size;
 	ucode->bootloader_phys_base = desc.imem_phys_base;
 	ucode->bootloader_size = desc.imem_load_size - desc.imem_sec_size;
 	ucode->ucode = ucode->bootloader + ucode->bootloader_size;
@@ -344,7 +527,7 @@ static int nvgpu_bios_parse_falcon_ucode_table(struct gk20a *g, u32 offset)
 	struct falcon_ucode_table_hdr_v1 hdr;
 	u32 i;
 
-	nvgpu_memcpy((u8 *)&hdr, &g->bios.data[offset], sizeof(hdr));
+	nvgpu_memcpy((u8 *)&hdr, &g->bios->data[offset], sizeof(hdr));
 	nvgpu_log_fn(g, "falcon ucode table ver %d size %d entrySize %d entryCount %d descVer %d descSize %d",
 			hdr.version, hdr.header_size,
 			hdr.entry_size, hdr.entry_count,
@@ -359,7 +542,7 @@ static int nvgpu_bios_parse_falcon_ucode_table(struct gk20a *g, u32 offset)
 	for (i = 0U; i < hdr.entry_count; i++) {
 		struct falcon_ucode_table_entry_v1 entry;
 
-		nvgpu_memcpy((u8 *)&entry, &g->bios.data[offset],
+		nvgpu_memcpy((u8 *)&entry, &g->bios->data[offset],
 			sizeof(entry));
 
 		nvgpu_log_fn(g, "falcon ucode table entry appid %x targetId %x descPtr %x",
@@ -371,12 +554,12 @@ static int nvgpu_bios_parse_falcon_ucode_table(struct gk20a *g, u32 offset)
 			int err;
 
 			err = nvgpu_bios_parse_falcon_ucode_desc(g,
-					&g->bios.devinit, entry.desc_ptr);
+					&g->bios->devinit, entry.desc_ptr);
 			if (err != 0) {
 				err = nvgpu_bios_parse_falcon_ucode_desc(g,
-					&g->bios.devinit,
+					&g->bios->devinit,
 					entry.desc_ptr +
-					 g->bios.expansion_rom_offset);
+					 g->bios->expansion_rom_offset);
 			}
 
 			if (err != 0) {
@@ -388,12 +571,12 @@ static int nvgpu_bios_parse_falcon_ucode_table(struct gk20a *g, u32 offset)
 			int err;
 
 			err = nvgpu_bios_parse_falcon_ucode_desc(g,
-					&g->bios.preos, entry.desc_ptr);
+					&g->bios->preos, entry.desc_ptr);
 			if (err != 0) {
 				err = nvgpu_bios_parse_falcon_ucode_desc(g,
-					&g->bios.preos,
+					&g->bios->preos,
 					entry.desc_ptr +
-					 g->bios.expansion_rom_offset);
+					 g->bios->expansion_rom_offset);
 			}
 
 			if (err != 0) {
@@ -418,7 +601,7 @@ static void nvgpu_bios_parse_falcon_data_v2(struct gk20a *g, u32 offset)
 	struct falcon_data_v2 falcon_data;
 	int err;
 
-	nvgpu_memcpy((u8 *)&falcon_data, &g->bios.data[offset],
+	nvgpu_memcpy((u8 *)&falcon_data, &g->bios->data[offset],
 		sizeof(falcon_data));
 	nvgpu_log_fn(g, "falcon ucode table ptr %x",
 			falcon_data.falcon_ucode_table_ptr);
@@ -427,7 +610,7 @@ static void nvgpu_bios_parse_falcon_data_v2(struct gk20a *g, u32 offset)
 	if (err != 0) {
 		err = nvgpu_bios_parse_falcon_ucode_table(g,
 				falcon_data.falcon_ucode_table_ptr +
-			g->bios.expansion_rom_offset);
+			g->bios->expansion_rom_offset);
 	}
 
 	if (err != 0) {
@@ -446,14 +629,14 @@ void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g,
 
 		if (ptoken->token_id == TOKEN_ID_VIRT_PTRS) {
 			perf_table_id_offset =
-				*((u16 *)((uintptr_t)g->bios.data +
+				*((u16 *)((uintptr_t)g->bios->data +
 					  ptoken->data_ptr +
 					  (U16(table_id) *
 					   U16(PERF_PTRS_WIDTH_16))));
 			data_size = PERF_PTRS_WIDTH_16;
 		} else {
 			perf_table_id_offset =
-				*((u32 *)((uintptr_t)g->bios.data +
+				*((u32 *)((uintptr_t)g->bios->data +
 					  ptoken->data_ptr +
 					  (U16(table_id) *
 					   U16(PERF_PTRS_WIDTH))));
@@ -472,13 +655,13 @@ void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g,
 
 		if (perf_table_id_offset != 0U) {
 			/* check if perf_table_id_offset is beyond base rom */
-			if (perf_table_id_offset > g->bios.base_rom_size) {
+			if (perf_table_id_offset > g->bios->base_rom_size) {
 				perf_table_ptr =
-					&g->bios.data[g->bios.expansion_rom_offset +
+					&g->bios->data[g->bios->expansion_rom_offset +
 						perf_table_id_offset];
 			} else {
 				perf_table_ptr =
-					&g->bios.data[perf_table_id_offset];
+					&g->bios->data[perf_table_id_offset];
 			}
 		} else {
 			nvgpu_warn(g, "PERF TABLE ID %d is NULL",
@@ -498,7 +681,7 @@ static void nvgpu_bios_parse_bit(struct gk20a *g, u32 offset)
 	u32 i;
 
 	nvgpu_log_fn(g, " ");
-	nvgpu_memcpy((u8 *)&bit, &g->bios.data[offset], sizeof(bit));
+	nvgpu_memcpy((u8 *)&bit, &g->bios->data[offset], sizeof(bit));
 
 	nvgpu_log_info(g, "BIT header: %04x %08x", bit.id, bit.signature);
 	nvgpu_log_info(g, "tokens: %d entries * %d bytes",
@@ -506,7 +689,7 @@ static void nvgpu_bios_parse_bit(struct gk20a *g, u32 offset)
 
 	offset += bit.header_size;
 	for (i = 0U; i < bit.token_entries; i++) {
-		nvgpu_memcpy((u8 *)&token, &g->bios.data[offset],
+		nvgpu_memcpy((u8 *)&token, &g->bios->data[offset],
 			sizeof(token));
 
 		nvgpu_log_info(g, "BIT token id %d ptr %d size %d ver %d",
@@ -527,19 +710,19 @@ static void nvgpu_bios_parse_bit(struct gk20a *g, u32 offset)
 			}
 			break;
 		case TOKEN_ID_PERF_PTRS:
-			g->bios.perf_token =
+			g->bios->perf_token =
 				(struct bit_token *)
-					((uintptr_t)g->bios.data + offset);
+					((uintptr_t)g->bios->data + offset);
 			break;
 		case TOKEN_ID_CLOCK_PTRS:
-			g->bios.clock_token =
+			g->bios->clock_token =
 				(struct bit_token *)
-					((uintptr_t)g->bios.data + offset);
+					((uintptr_t)g->bios->data + offset);
 			break;
 		case TOKEN_ID_VIRT_PTRS:
-			g->bios.virt_token =
+			g->bios->virt_token =
 				(struct bit_token *)
-					((uintptr_t)g->bios.data + offset);
+					((uintptr_t)g->bios->data + offset);
 			break;
 		case TOKEN_ID_MEMORY_PTRS:
 			nvgpu_bios_parse_memory_ptrs(g, token.data_ptr,
@@ -558,7 +741,7 @@ static void nvgpu_bios_parse_bit(struct gk20a *g, u32 offset)
 
 static u32 nvgpu_bios_readbyte_impl(struct gk20a *g, u32 offset)
 {
-	return g->bios.data[offset];
+	return g->bios->data[offset];
 }
 
 u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset)
diff --git a/drivers/gpu/nvgpu/common/vbios/bios_sw_gp106.c b/drivers/gpu/nvgpu/common/vbios/bios_sw_gp106.c
deleted file mode 100644
index 574bebc7d..000000000
--- a/drivers/gpu/nvgpu/common/vbios/bios_sw_gp106.c
+++ /dev/null
@@ -1,305 +0,0 @@
-/*
- * Copyright (c) 2015-2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <nvgpu/bios.h>
-#include <nvgpu/kmem.h>
-#include <nvgpu/nvgpu_common.h>
-#include <nvgpu/timers.h>
-#include <nvgpu/falcon.h>
-#include <nvgpu/enabled.h>
-#include <nvgpu/io.h>
-#include <nvgpu/gk20a.h>
-
-#include "hal/top/top_gp106.h"
-
-#include "bios_sw_gp106.h"
-
-#define PMU_BOOT_TIMEOUT_DEFAULT	100 /* usec */
-#define PMU_BOOT_TIMEOUT_MAX		2000000 /* usec */
-#define BIOS_OVERLAY_NAME "bios-%04x.rom"
-#define BIOS_OVERLAY_NAME_FORMATTED "bios-xxxx.rom"
-#define ROM_FILE_PAYLOAD_OFFSET 0xa00
-#define BIOS_SIZE 0x90000
-
-int gp106_bios_devinit(struct gk20a *g)
-{
-	int err = 0;
-	bool devinit_completed;
-	struct nvgpu_timeout timeout;
-	u32 top_scratch1_reg;
-
-	nvgpu_log_fn(g, " ");
-
-	if (nvgpu_falcon_reset(g->pmu->flcn) != 0) {
-		err = -ETIMEDOUT;
-		goto out;
-	}
-
-	err = nvgpu_falcon_copy_to_imem(g->pmu->flcn,
-			g->bios.devinit.bootloader_phys_base,
-			g->bios.devinit.bootloader,
-			g->bios.devinit.bootloader_size,
-			0, 0, g->bios.devinit.bootloader_phys_base >> 8);
-	if (err != 0) {
-		nvgpu_err(g, "bios devinit bootloader copy failed %d", err);
-		goto out;
-	}
-
-	err = nvgpu_falcon_copy_to_imem(g->pmu->flcn, g->bios.devinit.phys_base,
-			g->bios.devinit.ucode,
-			g->bios.devinit.size,
-			0, 1, g->bios.devinit.phys_base >> 8);
-	if (err != 0) {
-		nvgpu_err(g, "bios devinit ucode copy failed %d", err);
-		goto out;
-	}
-
-	err = nvgpu_falcon_copy_to_dmem(g->pmu->flcn, g->bios.devinit.dmem_phys_base,
-			g->bios.devinit.dmem,
-			g->bios.devinit.dmem_size,
-			0);
-	if (err != 0) {
-		nvgpu_err(g, "bios devinit dmem copy failed %d", err);
-		goto out;
-	}
-
-	err = nvgpu_falcon_copy_to_dmem(g->pmu->flcn, g->bios.devinit_tables_phys_base,
-			g->bios.devinit_tables,
-			g->bios.devinit_tables_size,
-			0);
-	if (err != 0) {
-		nvgpu_err(g, "fbios devinit tables copy failed %d", err);
-		goto out;
-	}
-
-	err = nvgpu_falcon_copy_to_dmem(g->pmu->flcn, g->bios.devinit_script_phys_base,
-			g->bios.bootscripts,
-			g->bios.bootscripts_size,
-			0);
-	if (err != 0) {
-		nvgpu_err(g, "bios devinit bootscripts copy failed %d", err);
-		goto out;
-	}
-
-	err = nvgpu_falcon_bootstrap(g->pmu->flcn,
-					g->bios.devinit.code_entry_point);
-	if (err != 0) {
-		nvgpu_err(g, "falcon bootstrap failed %d", err);
-		goto out;
-	}
-
-	nvgpu_timeout_init(g, &timeout,
-			   PMU_BOOT_TIMEOUT_MAX /
-				PMU_BOOT_TIMEOUT_DEFAULT,
-			   NVGPU_TIMER_RETRY_TIMER);
-	do {
-		top_scratch1_reg = g->ops.top.read_top_scratch1_reg(g);
-		devinit_completed = ((g->ops.falcon.is_falcon_cpu_halted(
-				g->pmu->flcn) != 0U) &&
-				(g->ops.top.top_scratch1_devinit_completed(g,
-				top_scratch1_reg)) != 0U);
-
-		nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT);
-	} while (!devinit_completed && (nvgpu_timeout_expired(&timeout) == 0));
-
-	if (nvgpu_timeout_peek_expired(&timeout) != 0) {
-		err = -ETIMEDOUT;
-		goto out;
-	}
-
-	err = nvgpu_falcon_clear_halt_intr_status(g->pmu->flcn,
-		nvgpu_get_poll_timeout(g));
-	if (err != 0) {
-		nvgpu_err(g, "falcon_clear_halt_intr_status failed %d", err);
-		goto out;
-	}
-
-out:
-	nvgpu_log_fn(g, "done");
-	return err;
-}
-
-int gp106_bios_preos_wait_for_halt(struct gk20a *g)
-{
-	return nvgpu_falcon_wait_for_halt(g->pmu->flcn,
-					PMU_BOOT_TIMEOUT_MAX / 1000);
-}
-
-int gp106_bios_preos(struct gk20a *g)
-{
-	int err = 0;
-
-	nvgpu_log_fn(g, " ");
-
-	if (nvgpu_falcon_reset(g->pmu->flcn) != 0) {
-		err = -ETIMEDOUT;
-		goto out;
-	}
-
-	if (g->ops.bios.preos_reload_check != NULL) {
-		g->ops.bios.preos_reload_check(g);
-	}
-
-	err = nvgpu_falcon_copy_to_imem(g->pmu->flcn,
-			g->bios.preos.bootloader_phys_base,
-			g->bios.preos.bootloader,
-			g->bios.preos.bootloader_size,
-			0, 0, g->bios.preos.bootloader_phys_base >> 8);
-	if (err != 0) {
-		nvgpu_err(g, "bios preos bootloader copy failed %d", err);
-		goto out;
-	}
-
-	err = nvgpu_falcon_copy_to_imem(g->pmu->flcn, g->bios.preos.phys_base,
-			g->bios.preos.ucode,
-			g->bios.preos.size,
-			0, 1, g->bios.preos.phys_base >> 8);
-	if (err != 0) {
-		nvgpu_err(g, "bios preos ucode copy failed %d", err);
-		goto out;
-	}
-
-	err = nvgpu_falcon_copy_to_dmem(g->pmu->flcn, g->bios.preos.dmem_phys_base,
-			g->bios.preos.dmem,
-			g->bios.preos.dmem_size,
-			0);
-	if (err != 0) {
-		nvgpu_err(g, "bios preos dmem copy failed %d", err);
-		goto out;
-	}
-
-	err = nvgpu_falcon_bootstrap(g->pmu->flcn,
-					g->bios.preos.code_entry_point);
-	if (err != 0) {
-		nvgpu_err(g, "falcon bootstrap failed %d", err);
-		goto out;
-	}
-
-	err = g->ops.bios.preos_wait_for_halt(g);
-	if (err != 0) {
-		nvgpu_err(g, "preos_wait_for_halt failed %d", err);
-		goto out;
-	}
-
-	err = nvgpu_falcon_clear_halt_intr_status(g->pmu->flcn,
-			nvgpu_get_poll_timeout(g));
-	if (err != 0) {
-		nvgpu_err(g, "falcon_clear_halt_intr_status failed %d", err);
-		goto out;
-	}
-
-out:
-	nvgpu_log_fn(g, "done");
-	return err;
-}
-
-int gp106_bios_init(struct gk20a *g)
-{
-	unsigned int i;
-	int err;
-
-	nvgpu_log_fn(g, " ");
-
-	if (g->bios_is_init) {
-		return 0;
-	}
-
-	nvgpu_log_info(g, "reading bios from EEPROM");
-	g->bios.size = BIOS_SIZE;
-	g->bios.data = nvgpu_vmalloc(g, BIOS_SIZE);
-	if (g->bios.data == NULL) {
-		return -ENOMEM;
-	}
-
-	if (g->ops.xve.disable_shadow_rom != NULL) {
-		g->ops.xve.disable_shadow_rom(g);
-	}
-	for (i = 0U; i < g->bios.size/4U; i++) {
-		u32 val = be32_to_cpu(gk20a_readl(g, 0x300000U + i*4U));
-
-		g->bios.data[(i*4U)] = (val >> 24U) & 0xffU;
-		g->bios.data[(i*4U)+1U] = (val >> 16U) & 0xffU;
-		g->bios.data[(i*4U)+2U] = (val >> 8U) & 0xffU;
-		g->bios.data[(i*4U)+3U] = val & 0xffU;
-	}
-	if (g->ops.xve.enable_shadow_rom != NULL) {
-		g->ops.xve.enable_shadow_rom(g);
-	}
-
-	err = nvgpu_bios_parse_rom(g);
-	if (err != 0) {
-		goto free_firmware;
-	}
-
-	if (g->bios.vbios_version < g->vbios_min_version) {
-		nvgpu_err(g, "unsupported VBIOS version %08x",
-				g->bios.vbios_version);
-		err = -EINVAL;
-		goto free_firmware;
-	} else {
-		nvgpu_info(g, "VBIOS version %08x", g->bios.vbios_version);
-	}
-
-	if ((g->vbios_compatible_version != 0U) &&
-	    (g->bios.vbios_version != g->vbios_compatible_version)) {
-		nvgpu_err(g, "VBIOS version %08x is not officially supported.",
-			g->bios.vbios_version);
-		nvgpu_err(g, "Update to VBIOS %08x, or use at your own risks.",
-			g->vbios_compatible_version);
-	}
-
-	nvgpu_log_fn(g, "done");
-
-	if (g->ops.bios.devinit != NULL) {
-		err = g->ops.bios.devinit(g);
-		if (err != 0) {
-			nvgpu_err(g, "devinit failed");
-			goto free_firmware;
-		}
-	}
-
-	if (nvgpu_is_enabled(g, NVGPU_PMU_RUN_PREOS) &&
-	    (g->ops.bios.preos != NULL)) {
-		err = g->ops.bios.preos(g);
-		if (err != 0) {
-			nvgpu_err(g, "pre-os failed");
-			goto free_firmware;
-		}
-	}
-
-	if (g->ops.bios.verify_devinit != NULL) {
-		err = g->ops.bios.verify_devinit(g);
-		if (err != 0) {
-			nvgpu_err(g, "devinit status verification failed");
-			goto free_firmware;
-		}
-	}
-
-	g->bios_is_init = true;
-
-	return 0;
-free_firmware:
-	if (g->bios.data != NULL) {
-		nvgpu_vfree(g, g->bios.data);
-	}
-	return err;
-}
diff --git a/drivers/gpu/nvgpu/common/vbios/bios_sw_gp106.h b/drivers/gpu/nvgpu/common/vbios/bios_sw_gp106.h
deleted file mode 100644
index 986684185..000000000
--- a/drivers/gpu/nvgpu/common/vbios/bios_sw_gp106.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef NVGPU_BIOS_SW_GP106_H
-#define NVGPU_BIOS_SW_GP106_H
-
-struct gk20a;
-
-int gp106_bios_init(struct gk20a *g);
-int gp106_bios_preos_wait_for_halt(struct gk20a *g);
-int gp106_bios_devinit(struct gk20a *g);
-int gp106_bios_preos(struct gk20a *g);
-
-#endif /* NVGPU_BIOS_SW_GP106_H */
diff --git a/drivers/gpu/nvgpu/common/vbios/bios_sw_gv100.c b/drivers/gpu/nvgpu/common/vbios/bios_sw_gv100.c
index 7bcdeb32e..9dcbaa667 100644
--- a/drivers/gpu/nvgpu/common/vbios/bios_sw_gv100.c
+++ b/drivers/gpu/nvgpu/common/vbios/bios_sw_gv100.c
@@ -26,9 +26,10 @@
 #include <nvgpu/io.h>
 #include <nvgpu/gk20a.h>
 
-#include "bios_sw_gp106.h"
 #include "bios_sw_gv100.h"
 
+#define BIOS_SIZE 0x90000
+
 #define PMU_BOOT_TIMEOUT_DEFAULT	100U /* usec */
 #define PMU_BOOT_TIMEOUT_MAX		2000000U /* usec */
 
@@ -104,3 +105,280 @@ int gv100_bios_preos_wait_for_halt(struct gk20a *g)
 
 	return err;
 }
+
+int gv100_bios_devinit(struct gk20a *g)
+{
+	int err = 0;
+	bool devinit_completed;
+	struct nvgpu_timeout timeout;
+	u32 top_scratch1_reg;
+
+	nvgpu_log_fn(g, " ");
+
+	if (nvgpu_falcon_reset(g->pmu->flcn) != 0) {
+		err = -ETIMEDOUT;
+		goto out;
+	}
+
+	err = nvgpu_falcon_copy_to_imem(g->pmu->flcn,
+			g->bios->devinit.bootloader_phys_base,
+			g->bios->devinit.bootloader,
+			g->bios->devinit.bootloader_size,
+			0, 0, g->bios->devinit.bootloader_phys_base >> 8);
+	if (err != 0) {
+		nvgpu_err(g, "bios devinit bootloader copy failed %d", err);
+		goto out;
+	}
+
+	err = nvgpu_falcon_copy_to_imem(g->pmu->flcn, g->bios->devinit.phys_base,
+					g->bios->devinit.ucode,
+					g->bios->devinit.size,
+					0, 1, g->bios->devinit.phys_base >> 8);
+	if (err != 0) {
+		nvgpu_err(g, "bios devinit ucode copy failed %d", err);
+		goto out;
+	}
+
+	err = nvgpu_falcon_copy_to_dmem(g->pmu->flcn,
+				g->bios->devinit.dmem_phys_base,
+				g->bios->devinit.dmem,
+				g->bios->devinit.dmem_size,
+				0);
+	if (err != 0) {
+		nvgpu_err(g, "bios devinit dmem copy failed %d", err);
+		goto out;
+	}
+
+	err = nvgpu_falcon_copy_to_dmem(g->pmu->flcn,
+				g->bios->devinit_tables_phys_base,
+				g->bios->devinit_tables,
+				g->bios->devinit_tables_size,
+				0);
+	if (err != 0) {
+		nvgpu_err(g, "fbios devinit tables copy failed %d", err);
+		goto out;
+	}
+
+	err = nvgpu_falcon_copy_to_dmem(g->pmu->flcn,
+		g->bios->devinit_script_phys_base,
+		g->bios->bootscripts,
+		g->bios->bootscripts_size,
+		0);
+	if (err != 0) {
+		nvgpu_err(g, "bios devinit bootscripts copy failed %d", err);
+		goto out;
+	}
+
+	err = nvgpu_falcon_bootstrap(g->pmu->flcn,
+				g->bios->devinit.code_entry_point);
+	if (err != 0) {
+		nvgpu_err(g, "falcon bootstrap failed %d", err);
+		goto out;
+	}
+
+	nvgpu_timeout_init(g, &timeout,
+					PMU_BOOT_TIMEOUT_MAX /
+						PMU_BOOT_TIMEOUT_DEFAULT,
+					NVGPU_TIMER_RETRY_TIMER);
+	do {
+		top_scratch1_reg = g->ops.top.read_top_scratch1_reg(g);
+		devinit_completed = ((g->ops.falcon.is_falcon_cpu_halted(
+				g->pmu->flcn) != 0U) &&
+				(g->ops.top.top_scratch1_devinit_completed(g,
+				top_scratch1_reg)) != 0U);
+
+		nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT);
+	} while (!devinit_completed && (nvgpu_timeout_expired(&timeout) == 0));
+
+	if (nvgpu_timeout_peek_expired(&timeout) != 0) {
+		err = -ETIMEDOUT;
+		goto out;
+	}
+
+	err = nvgpu_falcon_clear_halt_intr_status(g->pmu->flcn,
+		nvgpu_get_poll_timeout(g));
+	if (err != 0) {
+		nvgpu_err(g, "falcon_clear_halt_intr_status failed %d", err);
+		goto out;
+	}
+
+out:
+	nvgpu_log_fn(g, "done");
+	return err;
+}
+
+int gv100_bios_init(struct gk20a *g)
+{
+	unsigned int i;
+	int err;
+
+	nvgpu_log_fn(g, " ");
+
+	if (g->bios_is_init) {
+		return 0;
+	}
+
+	nvgpu_log_info(g, "reading bios from EEPROM");
+	g->bios->size = BIOS_SIZE;
+	g->bios->data = nvgpu_vmalloc(g, BIOS_SIZE);
+	if (g->bios->data == NULL) {
+		return -ENOMEM;
+	}
+
+	if (g->ops.xve.disable_shadow_rom != NULL) {
+		g->ops.xve.disable_shadow_rom(g);
+	}
+
+	for (i = 0U; i < g->bios->size/4U; i++) {
+		u32 val = be32_to_cpu(gk20a_readl(g, 0x300000U + i*4U));
+
+		g->bios->data[(i*4U)] = (val >> 24U) & 0xffU;
+		g->bios->data[(i*4U)+1U] = (val >> 16U) & 0xffU;
+		g->bios->data[(i*4U)+2U] = (val >> 8U) & 0xffU;
+		g->bios->data[(i*4U)+3U] = val & 0xffU;
+	}
+
+	if (g->ops.xve.enable_shadow_rom != NULL) {
+		g->ops.xve.enable_shadow_rom(g);
+	}
+
+	err = nvgpu_bios_parse_rom(g);
+	if (err != 0) {
+		goto free_firmware;
+	}
+
+	if (g->bios->vbios_version < g->vbios_min_version) {
+		nvgpu_err(g, "unsupported VBIOS version %08x",
+					g->bios->vbios_version);
+		err = -EINVAL;
+		goto free_firmware;
+	} else {
+		nvgpu_info(g, "VBIOS version %08x", g->bios->vbios_version);
+	}
+
+	if ((g->vbios_compatible_version != 0U) &&
+		(g->bios->vbios_version != g->vbios_compatible_version)) {
+			nvgpu_err(g, "VBIOS version %08x is not officially supported.",
+			g->bios->vbios_version);
+			nvgpu_err(g, "Update to VBIOS %08x, or use at your own risks.",
+				g->vbios_compatible_version);
+	}
+
+	nvgpu_log_fn(g, "done");
+
+	err = nvgpu_bios_devinit(g, g->bios);
+	if (err != 0) {
+		nvgpu_err(g, "devinit failed");
+		goto free_firmware;
+	}
+
+	if (nvgpu_is_enabled(g, NVGPU_PMU_RUN_PREOS) &&
+		(g->bios->preos_bios != NULL)) {
+			err = g->bios->preos_bios(g);
+			if (err != 0) {
+				nvgpu_err(g, "pre-os failed");
+				goto free_firmware;
+			}
+	}
+
+	if (g->bios->verify_devinit != NULL) {
+		err = g->bios->verify_devinit(g);
+		if (err != 0) {
+				nvgpu_err(g, "devinit status verification failed");
+				goto free_firmware;
+		}
+	}
+
+	g->bios_is_init = true;
+
+	return 0;
+
+free_firmware:
+	if (g->bios->data != NULL) {
+			nvgpu_vfree(g, g->bios->data);
+	}
+	return err;
+}
+
+int gv100_bios_preos(struct gk20a *g)
+{
+	int err = 0;
+
+	nvgpu_log_fn(g, " ");
+
+	if (nvgpu_falcon_reset(g->pmu->flcn) != 0) {
+		err = -ETIMEDOUT;
+		goto out;
+	}
+
+	if (g->bios->preos_reload_check != NULL) {
+		g->bios->preos_reload_check(g);
+	}
+
+	err = nvgpu_falcon_copy_to_imem(g->pmu->flcn,
+		g->bios->preos.bootloader_phys_base,
+		g->bios->preos.bootloader,
+		g->bios->preos.bootloader_size,
+		0, 0, g->bios->preos.bootloader_phys_base >> 8);
+
+	if (err != 0) {
+		nvgpu_err(g, "bios preos bootloader copy failed %d", err);
+		goto out;
+	}
+
+	err = nvgpu_falcon_copy_to_imem(g->pmu->flcn, g->bios->preos.phys_base,
+		g->bios->preos.ucode,
+		g->bios->preos.size,
+		0, 1, g->bios->preos.phys_base >> 8);
+
+	if (err != 0) {
+		nvgpu_err(g, "bios preos ucode copy failed %d", err);
+		goto out;
+	}
+
+	err = nvgpu_falcon_copy_to_dmem(g->pmu->flcn, g->bios->preos.dmem_phys_base,
+		g->bios->preos.dmem,
+		g->bios->preos.dmem_size,
+		0);
+
+	if (err != 0) {
+		nvgpu_err(g, "bios preos dmem copy failed %d", err);
+		goto out;
+	}
+
+	err = nvgpu_falcon_bootstrap(g->pmu->flcn,
+				g->bios->preos.code_entry_point);
+
+	if (err != 0) {
+		nvgpu_err(g, "falcon bootstrap failed %d", err);
+		goto out;
+	}
+
+	err = nvgpu_bios_preos_wait_for_halt(g, g->bios);
+	if (err != 0) {
+		nvgpu_err(g, "preos_wait_for_halt failed %d", err);
+		goto out;
+	}
+
+	err = nvgpu_falcon_clear_halt_intr_status(g->pmu->flcn,
+			nvgpu_get_poll_timeout(g));
+	if (err != 0) {
+		nvgpu_err(g, "falcon_clear_halt_intr_status failed %d", err);
+		goto out;
+	}
+
+out:
+	nvgpu_log_fn(g, "done");
+	return err;
+}
+
+void nvgpu_gv100_bios_sw_init(struct gk20a *g,
+		struct nvgpu_bios *bios)
+{
+	bios->init = gv100_bios_init;
+	bios->preos_wait_for_halt = gv100_bios_preos_wait_for_halt;
+	bios->preos_reload_check = gv100_bios_preos_reload_check;
+	bios->preos_bios = gv100_bios_preos;
+	bios->devinit_bios = gv100_bios_devinit;
+	bios->verify_devinit = NULL;
+}
diff --git a/drivers/gpu/nvgpu/common/vbios/bios_sw_gv100.h b/drivers/gpu/nvgpu/common/vbios/bios_sw_gv100.h
index 123234447..aff9ee602 100644
--- a/drivers/gpu/nvgpu/common/vbios/bios_sw_gv100.h
+++ b/drivers/gpu/nvgpu/common/vbios/bios_sw_gv100.h
@@ -24,8 +24,14 @@
 #define NVGPU_BIOS_SW_GV100_H
 
 struct gk20a;
+struct nvgpu_bios;
 
 void gv100_bios_preos_reload_check(struct gk20a *g);
 int gv100_bios_preos_wait_for_halt(struct gk20a *g);
+int gv100_bios_devinit(struct gk20a *g);
+int gv100_bios_preos(struct gk20a *g);
+int gv100_bios_init(struct gk20a *g);
+void nvgpu_gv100_bios_sw_init(struct gk20a *g,
+		struct nvgpu_bios *bios);
 
 #endif /* NVGPU_BIOS_SW_GV100_H */
diff --git a/drivers/gpu/nvgpu/common/vbios/bios_sw_tu104.c b/drivers/gpu/nvgpu/common/vbios/bios_sw_tu104.c
index ca9e611bc..101a1f969 100644
--- a/drivers/gpu/nvgpu/common/vbios/bios_sw_tu104.c
+++ b/drivers/gpu/nvgpu/common/vbios/bios_sw_tu104.c
@@ -25,8 +25,8 @@
 #include <nvgpu/io.h>
 #include <nvgpu/gk20a.h>
 
+#include "bios_sw_gv100.h"
 #include "bios_sw_tu104.h"
-#include "bios_sw_gp106.h"
 
 #define NV_DEVINIT_VERIFY_TIMEOUT_MS		1000U
 #define NV_DEVINIT_VERIFY_TIMEOUT_DELAY_US	10U
@@ -71,5 +71,17 @@ int tu104_bios_init(struct gk20a *g)
 		return 0;
 	}
 
-	return gp106_bios_init(g);
+	return gv100_bios_init(g);
 }
+
+void nvgpu_tu104_bios_sw_init(struct gk20a *g,
+		struct nvgpu_bios *bios)
+{
+	bios->init = tu104_bios_init;
+	bios->preos_wait_for_halt = NULL;
+	bios->preos_reload_check = NULL;
+	bios->preos_bios = NULL;
+	bios->devinit_bios = NULL;
+	bios->verify_devinit = tu104_bios_verify_devinit;
+}
+
diff --git a/drivers/gpu/nvgpu/common/vbios/bios_sw_tu104.h b/drivers/gpu/nvgpu/common/vbios/bios_sw_tu104.h
index 80c136409..041795a2f 100644
--- a/drivers/gpu/nvgpu/common/vbios/bios_sw_tu104.h
+++ b/drivers/gpu/nvgpu/common/vbios/bios_sw_tu104.h
@@ -27,5 +27,7 @@ struct gk20a;
 
 int tu104_bios_verify_devinit(struct gk20a *g);
 int tu104_bios_init(struct gk20a *g);
+void nvgpu_tu104_bios_sw_init(struct gk20a *g,
+		struct nvgpu_bios *bios);
 
 #endif /* NVGPU_BIOS_SW_TU104_H */
diff --git a/drivers/gpu/nvgpu/common/vbios/nvlink_bios.c b/drivers/gpu/nvgpu/common/vbios/nvlink_bios.c
index fa1b23f0c..2a3a5c844 100644
--- a/drivers/gpu/nvgpu/common/vbios/nvlink_bios.c
+++ b/drivers/gpu/nvgpu/common/vbios/nvlink_bios.c
@@ -30,12 +30,12 @@ int nvgpu_bios_get_nvlink_config_data(struct gk20a *g)
 	int ret = 0;
 	struct nvlink_config_data_hdr_v1 config;
 
-	if (g->bios.nvlink_config_data_offset == 0U) {
+	if (g->bios->nvlink_config_data_offset == 0U) {
 		return -EINVAL;
 	}
 
 	nvgpu_memcpy((u8 *)&config,
-		&g->bios.data[g->bios.nvlink_config_data_offset],
+		&g->bios->data[g->bios->nvlink_config_data_offset],
 		sizeof(config));
 
 	if (config.version != NVLINK_CONFIG_DATA_HDR_VER_10) {
@@ -78,7 +78,8 @@ int nvgpu_bios_get_lpwr_nvlink_table_hdr(struct gk20a *g)
 	u8 *lpwr_nvlink_tbl_hdr_ptr = NULL;
 
 	lpwr_nvlink_tbl_hdr_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-					g->bios.perf_token,
+					nvgpu_bios_get_bit_token(g,
+						NVGPU_BIOS_PERF_TOKEN),
 					LPWR_NVLINK_TABLE);
 	if (lpwr_nvlink_tbl_hdr_ptr == NULL) {
 		nvgpu_err(g, "Invalid pointer to LPWR_NVLINK_TABLE\n");
diff --git a/drivers/gpu/nvgpu/common/xve/xve_gp106.c b/drivers/gpu/nvgpu/common/xve/xve_gp106.c
index b346e7bed..721f91513 100644
--- a/drivers/gpu/nvgpu/common/xve/xve_gp106.c
+++ b/drivers/gpu/nvgpu/common/xve/xve_gp106.c
@@ -26,8 +26,6 @@
 #include <nvgpu/timers.h>
 #include <nvgpu/gk20a.h>
 
-#include "common/vbios/bios_sw_gp106.h"
-
 #include "xve_gp106.h"
 
 #include <nvgpu/hw/gp106/hw_xp_gp106.h>
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv100.c b/drivers/gpu/nvgpu/hal/init/hal_gv100.c
index 2cec1c654..8400e5089 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gv100.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv100.c
@@ -154,7 +154,6 @@
 #include "hal/fifo/channel_gm20b.h"
 #include "hal/fifo/channel_gv11b.h"
 #include "hal/fifo/channel_gv100.h"
-#include "common/vbios/bios_sw_gp106.h"
 #include "common/vbios/bios_sw_gv100.h"
 
 #include "hal_gv100.h"
@@ -201,14 +200,6 @@ static void gv100_init_gpu_characteristics(struct gk20a *g)
 
 
 static const struct gpu_ops gv100_ops = {
-	.bios = {
-		.init = gp106_bios_init,
-		.preos_wait_for_halt = gv100_bios_preos_wait_for_halt,
-		.preos_reload_check = gv100_bios_preos_reload_check,
-		.devinit = gp106_bios_devinit,
-		.preos = gp106_bios_preos,
-		.verify_devinit = NULL,
-	},
 	.ltc = {
 		.determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
 		.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index 5294abde4..649486173 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -176,9 +176,6 @@
 
 #include "hal/clk/clk_gv100.h"
 
-#include "common/vbios/bios_sw_gp106.h"
-#include "common/vbios/bios_sw_tu104.h"
-
 #include "hal/fbpa/fbpa_tu104.h"
 #include "hal_tu104.h"
 #include "hal_tu104_litter.h"
@@ -224,12 +221,6 @@ static void tu104_init_gpu_characteristics(struct gk20a *g)
 
 static const struct gpu_ops tu104_ops = {
 	.bios = {
-		.init = tu104_bios_init,
-		.preos_wait_for_halt = NULL,
-		.preos_reload_check = NULL,
-		.devinit = NULL,
-		.preos = NULL,
-		.verify_devinit = tu104_bios_verify_devinit,
 		.get_aon_secure_scratch_reg = tu104_get_aon_secure_scratch_reg,
 	},
 	.ltc = {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h
index 5ffd8c832..dc51d51d0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h
@@ -30,6 +30,12 @@ struct gk20a;
 #define PERF_PTRS_WIDTH		U8(0x4)
 #define PERF_PTRS_WIDTH_16	U8(0x2)
 
+enum {
+	NVGPU_BIOS_CLOCK_TOKEN = 0,
+	NVGPU_BIOS_PERF_TOKEN,
+	NVGPU_BIOS_VIRT_TOKEN
+};
+
 enum {
 	CLOCKS_TABLE = 2,
 	CLOCK_PROGRAMMING_TABLE,
@@ -1390,6 +1396,60 @@ struct pci_ext_data_struct {
 	u8 flags;
 } __packed;
 
+struct nvgpu_bios_ucode {
+	u8 *bootloader;
+	u32 bootloader_phys_base;
+	u32 bootloader_size;
+	u8 *ucode;
+	u32 phys_base;
+	u32 size;
+	u8 *dmem;
+	u32 dmem_phys_base;
+	u32 dmem_size;
+	u32 code_entry_point;
+};
+
+struct nvgpu_bios {
+	u32 vbios_version;
+	u8 vbios_oem_version;
+
+	u8 *data;
+	size_t size;
+
+	struct nvgpu_bios_ucode devinit;
+	struct nvgpu_bios_ucode preos;
+
+	u8 *devinit_tables;
+	u32 devinit_tables_size;
+	u8 *bootscripts;
+	u32 bootscripts_size;
+
+	u8 mem_strap_data_count;
+	u16 mem_strap_xlat_tbl_ptr;
+
+	u32 condition_table_ptr;
+
+	u32 devinit_tables_phys_base;
+	u32 devinit_script_phys_base;
+
+	struct bit_token *perf_token;
+	struct bit_token *clock_token;
+	struct bit_token *virt_token;
+	u32 expansion_rom_offset;
+	u32 base_rom_size;
+
+	u32 nvlink_config_data_offset;
+	int (*init)(struct gk20a *g);
+	int (*preos_wait_for_halt)(struct gk20a *g);
+	void (*preos_reload_check)(struct gk20a *g);
+	int (*preos_bios)(struct gk20a *g);
+	int (*verify_devinit)(struct gk20a *g);
+	int (*devinit_bios)(struct gk20a *g);
+};
+int nvgpu_bios_devinit(struct gk20a *g, struct nvgpu_bios *bios);
+int nvgpu_bios_preos_wait_for_halt(struct gk20a *g, struct nvgpu_bios *bios);
+int nvgpu_bios_sw_init(struct gk20a *g, struct nvgpu_bios **bios);
+void nvgpu_bios_sw_deinit(struct gk20a *g, struct nvgpu_bios *bios);
 int nvgpu_bios_parse_rom(struct gk20a *g);
 u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset);
 s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset);
@@ -1397,5 +1457,9 @@ u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset);
 u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset);
 void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g,
 		struct bit_token *ptoken, u8 table_id);
-
+bool nvgpu_bios_check_dgpu(struct gk20a *g, u32 ver);
+u32  nvgpu_bios_get_vbios_version(struct gk20a *g);
+u8  nvgpu_bios_get_vbios_oem_version(struct gk20a *g);
+struct bit_token *nvgpu_bios_get_bit_token(struct gk20a *g,
+		u8 token_id);
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index de089f288..a02cea154 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -117,6 +117,7 @@ enum ctxsw_addr_type;
 #include <nvgpu/ltc.h>
 #include <nvgpu/nvgpu_err.h>
 #include <nvgpu/worker.h>
+#include <nvgpu/bios.h>
 #include <nvgpu/semaphore.h>
 #include <nvgpu/fifo.h>
 #include <nvgpu/unit.h>
@@ -1589,12 +1590,6 @@ struct gpu_ops {
 	} ptimer;
 
 	struct {
-		int (*init)(struct gk20a *g);
-		int (*preos_wait_for_halt)(struct gk20a *g);
-		void (*preos_reload_check)(struct gk20a *g);
-		int (*devinit)(struct gk20a *g);
-		int (*preos)(struct gk20a *g);
-		int (*verify_devinit)(struct gk20a *g);
 		u32 (*get_aon_secure_scratch_reg)(struct gk20a *g, u32 i);
 	} bios;
 
@@ -1836,51 +1831,6 @@ struct gpu_ops {
 	void (*semaphore_wakeup)(struct gk20a *g, bool post_events);
 };
 
-struct nvgpu_bios_ucode {
-	u8 *bootloader;
-	u32 bootloader_phys_base;
-	u32 bootloader_size;
-	u8 *ucode;
-	u32 phys_base;
-	u32 size;
-	u8 *dmem;
-	u32 dmem_phys_base;
-	u32 dmem_size;
-	u32 code_entry_point;
-};
-
-struct nvgpu_bios {
-	u32 vbios_version;
-	u8 vbios_oem_version;
-
-	u8 *data;
-	size_t size;
-
-	struct nvgpu_bios_ucode devinit;
-	struct nvgpu_bios_ucode preos;
-
-	u8 *devinit_tables;
-	u32 devinit_tables_size;
-	u8 *bootscripts;
-	u32 bootscripts_size;
-
-	u8 mem_strap_data_count;
-	u16 mem_strap_xlat_tbl_ptr;
-
-	u32 condition_table_ptr;
-
-	u32 devinit_tables_phys_base;
-	u32 devinit_script_phys_base;
-
-	struct bit_token *perf_token;
-	struct bit_token *clock_token;
-	struct bit_token *virt_token;
-	u32 expansion_rom_offset;
-	u32 base_rom_size;
-
-	u32 nvlink_config_data_offset;
-};
-
 struct nvgpu_gpu_params {
 	/* GPU architecture ID */
 	u32 gpu_arch;
@@ -2125,7 +2075,7 @@ struct gk20a {
 
 	u32 valid_tpc_mask[MAX_TPC_PG_CONFIGS];
 
-	struct nvgpu_bios bios;
+	struct nvgpu_bios *bios;
 	bool bios_is_init;
 
 	struct nvgpu_clk_arb *clk_arb;
diff --git a/drivers/gpu/nvgpu/os/linux/debug_bios.c b/drivers/gpu/nvgpu/os/linux/debug_bios.c
index c8ebb6a0e..a6da5a3aa 100644
--- a/drivers/gpu/nvgpu/os/linux/debug_bios.c
+++ b/drivers/gpu/nvgpu/os/linux/debug_bios.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018 NVIDIA Corporation.  All rights reserved.
+ * Copyright (C) 2018-2019 NVIDIA Corporation.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -25,11 +25,11 @@ static int bios_version_show(struct seq_file *s, void *unused)
 	struct gk20a *g = s->private;
 
 	seq_printf(s, "Version %02X.%02X.%02X.%02X.%02X\n",
-		(g->bios.vbios_version >> 24) & 0xFF,
-		(g->bios.vbios_version >> 16) & 0xFF,
-		(g->bios.vbios_version >> 8) & 0xFF,
-		(g->bios.vbios_version >> 0) & 0xFF,
-		(g->bios.vbios_oem_version) & 0xFF);
+		(g->bios->vbios_version >> 24) & 0xFF,
+		(g->bios->vbios_version >> 16) & 0xFF,
+		(g->bios->vbios_version >> 8) & 0xFF,
+		(g->bios->vbios_version >> 0) & 0xFF,
+		(g->bios->vbios_oem_version) & 0xFF);
 
 	return 0;
 }
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
index 3ed945bf5..b7cf393f2 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
@@ -332,8 +332,8 @@ gk20a_ctrl_ioctl_gpu_characteristics(
 	gpu.dma_copy_class =
 		g->ops.get_litter_value(g, GPU_LIT_DMA_COPY_CLASS);
 
-	gpu.vbios_version = g->bios.vbios_version;
-	gpu.vbios_oem_version = g->bios.vbios_oem_version;
+	gpu.vbios_version = nvgpu_bios_get_vbios_version(g);
+	gpu.vbios_oem_version = nvgpu_bios_get_vbios_oem_version(g);
 
 	gpu.big_page_size = nvgpu_mm_get_default_big_page_size(g);
 	gpu.pde_coverage_bit_count =